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CY7C1021BL-15ZXI

更新时间： 2024-11-26 02:54:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 320K
描述
1-Mbit (64K x 16) Static RAM

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CY7C1021BL-15ZXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP2,
针数：44Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.58最长访问时间：15 ns
JESD-30 代码：R-PDSO-G44长度：18.415 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：44字数：65536 words
字数代码：64000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.194 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL宽度：10.16 mm
Base Number Matches：1

CY7C1021BL-15ZXI 数据手册

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CY7C1021B  
1-Mbit (64K x 16) Static RAM  
automatic power-down feature that significantly reduces  
power consumption when deselected.  
Features  
• Temperature Ranges  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• High speed  
— tAA = 12 ns (Commercial & Industrial)  
— tAA = 15 ns (Automotive)  
• CMOS for optimum speed/power  
• Low active power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O9 to I/O16. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
— 770 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
• Available in Pb-free and non Pb-free 44-pin TSOP II and  
44-pin 400-mil-wide SOJ  
Functional Description[1]  
The CY7C1021B is a high-performance CMOS static RAM  
organized as 65,536 words by 16 bits. This device has an  
The CY7C1021B is available in standard 44-pin TSOP Type II  
and 44-pin 400-mil-wide SOJ packages.  
Logic Block Diagram  
DATA IN DRIVERS  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
64K x 16  
I/O1–I/O8  
RAM Array  
512 X 2048  
I/O9–I/O16  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05145 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 28, 2006  
[+] Feedback  
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CY7C1021BL-15ZXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1021B-15ZXI CYPRESS

完全替代

 1-Mbit (64K x 16) Static RAM
CY7C1021BNL-15ZXC CYPRESS

完全替代

 1-Mbit (64K x 16) Static RAM
CY7C1021BNL-15ZXI CYPRESS

类似代替

 1-Mbit (64K x 16) Static RAM

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