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CY7C1020V33-15VCT PDF预览

CY7C1020V33-15VCT

更新时间： 2024-11-05 13:07:11
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赛普拉斯 - CYPRESS /
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CY7C1020V33-15VCT 数据手册

 浏览型号CY7C1020V33-15VCT的Datasheet PDF文件第2页浏览型号CY7C1020V33-15VCT的Datasheet PDF文件第3页浏览型号CY7C1020V33-15VCT的Datasheet PDF文件第4页浏览型号CY7C1020V33-15VCT的Datasheet PDF文件第5页浏览型号CY7C1020V33-15VCT的Datasheet PDF文件第6页浏览型号CY7C1020V33-15VCT的Datasheet PDF文件第7页 
fax id: 1075  
CY7C1020V  
32K x 16 Static RAM  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
Features  
1
8
written into the location specified on the address pins (A  
0
• 3.3V operation (3.0V - 3.6V)  
• High speed  
through A ). If byte high enable (BHE) is LOW, then data from  
14  
I/O pins (I/O through I/O ) is written into the location speci-  
9
16  
fied on the address pins (A through A ).  
0
14  
— t = 10 ns  
AA  
Reading from the device is accomplished by taking chip en-  
able (CE) and output enable (OE) LOW while forcing the write  
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data  
from the memory location specified by the address pins will  
• Low active power  
— 540 mW (max., 12 ns)  
• Very Low standby power  
appear on I/O to I/O . If byte high enable (BHE) is LOW, then  
1
8
— 330 W (max., “L” version)  
µ
data from memory will appear on I/O to I/O . See the truth  
9
16  
• Automatic power-down when deselected  
• Independent Control of Upper and Lower bytes  
table at the back of this datasheet for a complete description  
of read and write modes.  
Available in 44-pin TSOP II and 400-mil SOJ  
•
The input/output pins (I/O through I/O ) are placed in a  
1
16  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Functional Description  
The CY7C1020V is a high-performance CMOS static RAM or-  
ganized as 32,768 words by 16 bits. This device has an auto-  
matic power-down feature that significantly reduces power  
consumption when deselected.  
The CY7C1020V is available in standard 44-pin TSOP type II  
and 400-mil-wide SOJ packages.  
Writing to the device is accomplished by taking chip enable  
(CE) and write enable (WE) inputs LOW. If byte low enable  
Logic Block Diagram  
Pin Configuration  
SOJ / TSOP II  
DATA IN DRIVERS  
Top View  
44  
NC  
1
2
3
4
A
1
0
A
43  
42  
41  
40  
39  
38  
A
A
A
A
14  
13  
12  
11  
A
2
A6  
A5  
OE  
5
6
BHE  
BLE  
I/O  
A4  
A3  
A2  
A1  
A0  
CE  
32K x 16  
RAM Array  
I/O1 – I/O8  
I/O9 – I/O16  
I/O  
7
1
16  
37  
36  
35  
34  
33  
I/O  
I/O  
8
I/O  
I/O  
2
3
15  
14  
13  
9
10  
I/O  
V
SS  
I/O  
4
CC  
V
11  
12  
SS  
V
V
CC  
I/O  
32  
31  
30  
29  
28  
27  
I/O  
I/O  
13  
5
6
7
8
12  
11  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
10  
9
COLUMN DECODER  
WE 17  
NC  
A
18  
19  
20  
21  
22  
10  
A
9
8
A
3
BHE  
26  
25  
A
4
WE  
CE  
OE  
A
A
5
A
A
7
24  
23  
6
NC  
NC  
BLE 1020V-1  
1020V-2  
Selection Guide  
7C1020V-10  
10  
7C1020V-12  
7C1020V-15  
7C1020V-20  
Maximum Access Time (ns)  
12  
120  
90  
1
15  
110  
80  
1
20  
100  
70  
1
Maximum Operating Current (mA)  
130  
100  
1
L
L
Maximum CMOS Standby Current (mA)  
0.1  
0.1  
0.1  
0.1  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
October 1996 – Revised April 13, 1998  
1234567...9

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