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CY7C1011DV33-10BVIT

更新时间： 2024-09-18 13:07:11
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赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
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CY7C1011DV33-10BVIT 数据手册

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CY7C1011DV33  
2-Mbit (128K x 16)Static RAM  
Features  
Functional Description  
• Pin-and function-compatible with CY7C1011CV33  
• High speed  
The CY7C1011DV33 is a high-performance CMOS Static  
RAM organized as 128K words by 16 bits.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
— tAA = 10 ns  
• Low active power  
— ICC = 90 mA @ 10 ns (Industrial)  
• Low CMOS standby power  
— ISB2 = 10 mA  
• Data Retention at 2.0 V  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Easy memory expansion with CE and OE features  
• Available in Lead-Free 44-pin TSOP II, and 48-ball VFBGA  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY7C1011DV33 is available in standard Lead-Free  
44-pin TSOP II with center power and ground pinout, as well  
as 48-ball fine-pitch ball grid array (VFBGA) packages  
.
Pin Configuration  
TSOP II  
Logic Block Diagram  
Top View  
INPUT BUFFER  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
0
A
A
2
7
A
1
OE  
A
1
A
2
BHE  
BLE  
I/O  
I/O  
I/O  
A
I/O0–I/O7  
0
A
3
CE  
A
4
128K X 16  
I/O  
7
0
15  
I/O8–I/O15  
A
5
37  
36  
35  
34  
33  
I/O  
I/O  
8
A
1
2
14  
6
9
A
13  
7
10  
11  
12  
13  
A
I/O  
V
SS  
I/O  
8
3
CC  
12  
V
SS  
V
V
CC  
32  
I/O  
I/O  
4
5
6
7
11  
10  
COLUMN  
DECODER  
31  
30  
29  
28  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
14  
15  
16  
9
8
WE 17  
NC  
A
18  
16  
15  
27  
26  
25  
A
8
A
BHE  
19  
20  
21  
22  
A
9
10  
11  
WE  
CE  
OE  
A
14  
A
A
A
12  
24  
23  
13  
A
NC  
BLE  
Note  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com  
Cypress Semiconductor Corporation  
Document #: 38-05609 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 14, 2006  
[+] Feedback  
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