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CY7C09159-12AI PDF预览

CY7C09159-12AI

更新时间: 2024-09-18 21:55:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
15页 454K
描述
8K/16K x 9 Synchronous Dual-Port Static RAM

CY7C09159-12AI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-100
针数:100Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.84Is Samacsys:N
最长访问时间:12 ns最大时钟频率 (fCLK):50 MHz
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:73728 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9功能数量:1
端口数量:2端子数量:100
字数:8192 words字数代码:8000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX9
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.0005 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.375 mA
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

CY7C09159-12AI 数据手册

 浏览型号CY7C09159-12AI的Datasheet PDF文件第2页浏览型号CY7C09159-12AI的Datasheet PDF文件第3页浏览型号CY7C09159-12AI的Datasheet PDF文件第4页浏览型号CY7C09159-12AI的Datasheet PDF文件第5页浏览型号CY7C09159-12AI的Datasheet PDF文件第6页浏览型号CY7C09159-12AI的Datasheet PDF文件第7页 
51  
fax id: 5218  
CY7C09159  
CY7C09169  
PRELIMINARY  
8K/16K x 9  
Synchronous Dual-Port Static RAM  
• High-speed clock to data access 6.5/7.5/12 ns (max.)  
• Low operating power  
Features  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
— Active= 200 mA (typical)  
— Standby= 0.05 mA (typical)  
• 2 Flow-Through/Pipelined devices  
— 8K x 9 organization (CY7C09159)  
— 16K x 9 organization (CY7C09169)  
• 3 Modes  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
— Shorten cycle times  
— Minimize bus noise  
— Flow-Through  
— Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Automatic power-down  
— Pipelined  
— Burst  
• Pipelined output mode on both ports allows fast  
100-MHz cycle time  
• Commercial and Industrial temperature ranges  
Available in 100-pin TQFP  
• 0.35-micron CMOS for optimum speed/power  
v
Logic Block Diagram  
R/W  
R/W  
OE  
L
R
OE  
L
R
CE  
CE  
CE  
CE  
0L  
1L  
0R  
1R  
1
1
0
0
0/1  
0/1  
1
0
0
1
0/1  
0/1  
FT/Pipe  
FT/Pipe  
L
R
9
9
I/O –I/O  
I/O –I/O  
0L  
8L  
0R  
8R  
I/O  
I/O  
Control  
Control  
13/14  
13/14  
[1]  
[1]  
A –A  
A –A  
0 12/13R  
0
12/13L  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLK  
CLK  
ADS  
L
R
R
R
R
True Dual-Ported  
RAM Array  
ADS  
L
CNTEN  
CNTEN  
L
CNTRST  
CNTRST  
L
Note:  
1. A0–A12 for 8K; A0–A13 for 16K.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
November 1997 - Revised June 5, 1998  

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