Datasheet > CY7C0853AV-100BBC

CY7C0853AV-100BBC

更新时间： 2024-09-18 04:02:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
31页	830K
描述
FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

CY7C0853AV-100BBC 数据手册

浏览型号CY7C0853AV-100BBC的Datasheet PDF文件第2页

浏览型号CY7C0853AV-100BBC的Datasheet PDF文件第3页

浏览型号CY7C0853AV-100BBC的Datasheet PDF文件第4页

浏览型号CY7C0853AV-100BBC的Datasheet PDF文件第5页

浏览型号CY7C0853AV-100BBC的Datasheet PDF文件第6页

浏览型号CY7C0853AV-100BBC的Datasheet PDF文件第7页

CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K

Synchronous Dual-Port RAM

x 36 and 128K/256K x 18

CY7C0850AV/CY7C0851AV

CY7C0852AV/CY7C0853AV

FLEx36 3.3V 32K/64K/128K/256K x 36

Synchronous Dual-Port RAM

Functional Description

Features

• True dual-ported memory cells that allow simultaneous

The FLEx36™ family includes 1M, 2M, 4M and 9M pipelined,

synchronous, true dual-port static RAMs that are high-speed,

low-power 3.3V CMOS. Two ports are provided, permitting

independent, simultaneous access to any location in memory.

The result of writing to the same location by more than one port

at the same time is undefined. Registers on control, address,

and data lines allow for minimal set-up and hold time.

During a Read operation, data is registered for decreased

cycle time. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally (more details to follow). The internal Write pulse width is

independent of the duration of the R/W input signal. The

internal Write pulse is self-timed to allow the shortest possible

cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle with chip enables asserted is required

to reactivate the outputs.

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

access of the same memory location

• Synchronous pipelined operation

• Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit

devices

• Pipelined output mode allows fast operation

• 0.18-micron CMOS for optimum speed and power

• High-speed clock to data access

• 3.3V low power

— Active as low as 225 mA (typ)

— Standby as low as 55 mA (typ)

• Mailbox function for message passing

• Global master reset

• Separate byte enables on both ports

• Commercial and industrial temperature ranges

• IEEE 1149.1-compatible JTAG boundary scan

• 172-ball FBGA (1 mm pitch) (15 mm × 15 mm)

• 176-pin TQFP (24 mm × 24 mm × 1.4 mm)

• Counter wrap around control

— Internal mask register controls counter wrap-around

— Counter-interrupt flags to indicate wrap-around

— Memory block retransmit operation

• Counter readback on address lines

• Mask register readback on address lines

The CY7C0853A device in this family has limited features.

Please see See “Address Counter and Mask Register

Operations^[10]” on page 8. for details.

• Dual Chip Enables on both ports for easy depth

expansion

Table 1. Product Selection Guide

1-Mbit

2-Mbit

4-Mbit

9-Mbit

Density

(32K x 36)

CY7C0850AV

167

(64K x 36)

(128K x 36)

(256K x 36)

Part Number

Max. Speed (MHz)

CY7C0851AV

CY7C0852AV

CY7C0853AV

167

4.0

225

167

4.0

225

133

4.7

270

Max. Access Time - Clock to Data (ns)

Typical operating current (mA)

Package

4.0

225

176TQFP

172FBGA

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-06070 Rev. *G

Revised August 15, 2005

12 3 4 5 6 7...31

中文翻译

下载PDF

CY7C0853AV-100BBC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C0853V-133BBXI	CYPRESS	完全替代	FLEx36â¢ 3.3 V 32 K / 64 K / 128 K / 256 K Ã
CY7C0853V-133BBI	CYPRESS	完全替代	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V-133BBC	CYPRESS	完全替代	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

与CY7C0853AV-100BBC相关器件

型号	品牌	获取价格	描述	数据表
CY7C0853AV-100BBI	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853AV-133BBC	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853AV-133BBI	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V-100BBC	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V-100BBI	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V-133BBC	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V-133BBI	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V-133BBXI	CYPRESS	获取价格	FLEx36â¢ 3.3 V 32 K / 64 K / 128 K / 256 K Ã
CY7C0853V-167BBC	CYPRESS	获取价格	Dual-Port SRAM, 256KX36, 4.4ns, CMOS, PBGA172, 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, BGA

与CY7C0853AV-100BBC相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

23
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

21
SL74HC10N：高性能三输入与非门解析
2024-09-03

96
AIC1781A 电池充电控制器深度解析
2024-09-03

87

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C0853AV-100BBC

CY7C0853AV-100BBC 数据手册

CY7C0853AV-100BBC 替代型号

与CY7C0853AV-100BBC相关器件

与CY7C0853AV-100BBC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C0853AV-100BBC

CY7C0853AV-100BBC 数据手册

CY7C0853AV-100BBC 替代型号

与CY7C0853AV-100BBC相关器件

与CY7C0853AV-100BBC相关文章

您还可以找

您在本页遇到什么问题？