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CY7C0852V-133BBI PDF预览

CY7C0852V-133BBI

更新时间： 2024-11-07 22:17:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
29页 764K
描述
FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

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中文翻译

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CY7C0852V-133BBI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：FBGA-172针数：172
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.75
最长访问时间：4.4 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
JESD-30 代码：S-PBGA-B172JESD-609代码：e0
长度：15 mm内存密度：4718592 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端口数量：2端子数量：172
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA172,14X14,40
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：220
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.25 mm最大待机电流：0.075 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15 mmBase Number Matches：1

CY7C0852V-133BBI 数据手册

 浏览型号CY7C0852V-133BBI的Datasheet PDF文件第2页浏览型号CY7C0852V-133BBI的Datasheet PDF文件第3页浏览型号CY7C0852V-133BBI的Datasheet PDF文件第4页浏览型号CY7C0852V-133BBI的Datasheet PDF文件第5页浏览型号CY7C0852V-133BBI的Datasheet PDF文件第6页浏览型号CY7C0852V-133BBI的Datasheet PDF文件第7页 
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K  
Synchronous Dual-Port RAM  
x 36 and 128K/256K x 18  
CY7C0850V/CY7C0851V  
CY7C0852V/CY7C0853V  
TM  
FLEx36 3.3V 32K/64K/128K/256K x 36  
Synchronous Dual-Port RAM  
Functional Description  
Features  
• True dual-ported memory cells that allow simultaneous  
The FLEx36 family includes 1M, 2M, 4M and 9M pipelined,  
synchronous, true dual-port static RAMs that are high-speed,  
low-power 3.3V CMOS. Two ports are provided, permitting  
independent, simultaneous access to any location in memory.  
The result of writing to the same location by more than one port  
at the same time is undefined. Registers on control, address,  
and data lines allow for minimal set-up and hold time.  
During a Read operation, data is registered for decreased  
cycle time. Each port contains a burst counter on the input  
address register. After externally loading the counter with the  
initial address, the counter will increment the address inter-  
nally (more details to follow). The internal Write pulse width is  
independent of the duration of the R/W input signal. The  
internal Write pulse is self-timed to allow the shortest possible  
cycle times.  
access of the same memory location  
• Synchronous pipelined operation  
• Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit  
devices  
• Pipelined output mode allows fast operation  
• 0.18-micron CMOS for optimum speed and power  
• High-speed clock to data access  
• 3.3V low power  
—Active as low as 225 mA (typ)  
— Standby as low as 55 mA (typ)  
• Mailbox function for message passing  
• Global master reset  
• Separate byte enables on both ports  
• Commercial and industrial temperature ranges  
• IEEE 1149.1-compatible JTAG boundary scan  
• 172-ball FBGA (1 mm pitch) (15 mm × 15 mm)  
• 176-pin TQFP (24 mm × 24 mm × 1.4 mm)  
• Counter wrap around control  
A HIGH on CE0 or LOW on CE1 for one clock cycle will power  
down the internal circuitry to reduce the static power  
consumption. One cycle with chip enables asserted is required  
to reactivate the outputs.  
Additional features include: readback of burst-counter internal  
address value on address lines, counter-mask registers to  
control the counter wrap-around, counter interrupt (CNTINT)  
flags, readback of mask register value on address lines,  
retransmit functionality, interrupt flags for message passing,  
JTAG for boundary scan, and asynchronous Master Reset  
(MRST).  
— Internal mask register controls counter wrap-around  
— Counter-interrupt flags to indicate wrap-around  
— Memory block retransmit operation  
• Counter readback on address lines  
• Mask register readback on address lines  
The CY7C0853 device in this family has limited features.  
Please see See “Address Counter and Mask Register  
Operations[10]” on page 8. for details.  
• Dual Chip Enables on both ports for easy depth  
expansion  
Table 1. Product Selection Guide  
Density  
1-Mbit  
2-Mbit  
4-Mbit  
9-Mbit  
(32K x 36)  
CY7C0850V  
167  
(64K x 36)  
(128K x 36)  
(256K x 36)  
CY7C0851V  
CY7C0852V  
CY7C0853V  
133  
Part Number  
Max. Speed (MHz)  
Max. Access Time - clock to Data (ns)  
Typical operating current (mA)  
Package  
167  
4.0  
167  
4.0  
4.0  
4.7  
225  
225  
225  
270  
176TQFP  
172FBGA  
176TQFP  
172FBGA  
176TQFP  
172FBGA  
172FBGA  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-06070 Rev. *D  
Revised June 24, 2004  
1234567...29

中文翻译

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CY7C0852V-133BBI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C0852V-133BBCT CYPRESS

完全替代

 Dual-Port SRAM, 128KX36, 4.4ns, CMOS, PBGA172, 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, FBG
CY7C0852AV-133BBI CYPRESS

完全替代

 FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0852V-133BBC CYPRESS

类似代替

 FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

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CY7C0853AV-100BBI CYPRESS

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 		FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853AV-133BBC CYPRESS

获取价格

 		FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853AV-133BBI CYPRESS

获取价格

 		FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853V CYPRESS

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 		FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

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