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CY7C0852AV PDF预览

CY7C0852AV

更新时间: 2024-11-07 04:53:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
31页 830K
描述
FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

CY7C0852AV 数据手册

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CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K  
Synchronous Dual-Port RAM  
x 36 and 128K/256K x 18  
CY7C0850AV/CY7C0851AV  
CY7C0852AV/CY7C0853AV  
TM  
FLEx36 3.3V 32K/64K/128K/256K x 36  
Synchronous Dual-Port RAM  
Functional Description  
Features  
• True dual-ported memory cells that allow simultaneous  
The FLEx36™ family includes 1M, 2M, 4M and 9M pipelined,  
synchronous, true dual-port static RAMs that are high-speed,  
low-power 3.3V CMOS. Two ports are provided, permitting  
independent, simultaneous access to any location in memory.  
The result of writing to the same location by more than one port  
at the same time is undefined. Registers on control, address,  
and data lines allow for minimal set-up and hold time.  
During a Read operation, data is registered for decreased  
cycle time. Each port contains a burst counter on the input  
address register. After externally loading the counter with the  
initial address, the counter will increment the address inter-  
nally (more details to follow). The internal Write pulse width is  
independent of the duration of the R/W input signal. The  
internal Write pulse is self-timed to allow the shortest possible  
cycle times.  
A HIGH on CE0 or LOW on CE1 for one clock cycle will power  
down the internal circuitry to reduce the static power  
consumption. One cycle with chip enables asserted is required  
to reactivate the outputs.  
Additional features include: readback of burst-counter internal  
address value on address lines, counter-mask registers to  
control the counter wrap-around, counter interrupt (CNTINT)  
flags, readback of mask register value on address lines,  
retransmit functionality, interrupt flags for message passing,  
JTAG for boundary scan, and asynchronous Master Reset  
(MRST).  
access of the same memory location  
• Synchronous pipelined operation  
• Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit  
devices  
• Pipelined output mode allows fast operation  
• 0.18-micron CMOS for optimum speed and power  
• High-speed clock to data access  
• 3.3V low power  
— Active as low as 225 mA (typ)  
— Standby as low as 55 mA (typ)  
• Mailbox function for message passing  
• Global master reset  
• Separate byte enables on both ports  
• Commercial and industrial temperature ranges  
• IEEE 1149.1-compatible JTAG boundary scan  
• 172-ball FBGA (1 mm pitch) (15 mm × 15 mm)  
• 176-pin TQFP (24 mm × 24 mm × 1.4 mm)  
• Counter wrap around control  
— Internal mask register controls counter wrap-around  
— Counter-interrupt flags to indicate wrap-around  
— Memory block retransmit operation  
• Counter readback on address lines  
• Mask register readback on address lines  
The CY7C0853A device in this family has limited features.  
Please see See “Address Counter and Mask Register  
Operations[10]” on page 8. for details.  
• Dual Chip Enables on both ports for easy depth  
expansion  
Table 1. Product Selection Guide  
1-Mbit  
2-Mbit  
4-Mbit  
9-Mbit  
Density  
(32K x 36)  
CY7C0850AV  
167  
(64K x 36)  
(128K x 36)  
(256K x 36)  
Part Number  
Max. Speed (MHz)  
CY7C0851AV  
CY7C0852AV  
CY7C0853AV  
167  
4.0  
225  
167  
4.0  
225  
133  
4.7  
270  
Max. Access Time - Clock to Data (ns)  
Typical operating current (mA)  
Package  
4.0  
225  
176TQFP  
176TQFP  
176TQFP  
172FBGA  
172FBGA  
172FBGA  
172FBGA  
Cypress Semiconductor Corporation  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Document #: 38-06070 Rev. *G  
Revised August 15, 2005  

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