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CY7C0851V25 PDF预览

CY7C0851V25

更新时间: 2024-11-07 21:21:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
6页 193K
描述
SRAM

CY7C0851V25 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.8
Base Number Matches:1

CY7C0851V25 数据手册

 浏览型号CY7C0851V25的Datasheet PDF文件第2页浏览型号CY7C0851V25的Datasheet PDF文件第3页浏览型号CY7C0851V25的Datasheet PDF文件第4页浏览型号CY7C0851V25的Datasheet PDF文件第5页浏览型号CY7C0851V25的Datasheet PDF文件第6页 
851V25  
52V25  
CY7C0851V25  
CY7C0852V25  
ADVANCE INFORMATION  
2.5V 64K/128K x 36  
Sync Dual-Port Static RAM  
Features  
Functional Description  
True Dual-Ported memory cellsthatallow simultaneous  
access of the same memory location  
• Sync. Pipelined 4.5 Megabit devices  
64K x 36 organization (CY7C0851V25)  
The CY7C0851V25/CY7C0852V25 is a 4.5-Megabit pipelined  
synchronous true dual-port Static RAM. This is a high-speed,  
low-power 2.5V CMOS dual-port static RAM. Two ports are  
provided, permitting independent, simultaneous access for  
reads from any location in memory. A particular port can write  
to a certain location while the other port is reading that location  
simultaneously. The result of writing to the same location by  
more than one port at the same time is undefined. Registers  
on control, address, and data lines allow for minimal set-up  
and hold time.  
128K x 36 organization (CY7C0852V25)  
• Pipelined output mode allows fast 100-MHz operation  
• 0.18-micron CMOS for optimum speed/power  
• High-speed clock to data access: 5 ns (max.)  
• 2.5V Low operating power  
During a read operation, data is registered for decreased cycle  
Active = 150 mA (typical)  
time. Clock to data valid t  
= 5 ns. Each port contains a burst  
CD2  
Standby = 10 mA (typical)  
counter on the input address register. After externally loading  
the counter with the initial address the counter will self-incre-  
ment the address internally (more details to follow). The inter-  
nal write pulse width is independent of the duration of the R/W  
input signal. The internal write pulse is self-timed to allow the  
shortest possible cycle times.  
• HSTL class 1 I/O (0.75 Vref)  
• Counter wraparound control  
Internal mask register controls counter wraparound  
Counter-Interrupt flags to indicate wraparound  
Memory Block Retransmit Operation  
• Counter readback on address lines  
• Mask register readback on address lines  
• Interrupt flags for message passing  
• Global Master reset  
• Width and Depth expansion capabilities  
• Dual Chip Enables on both ports for easy depth expan-  
sion  
A HIGH on CE0 or LOW on CE1 for one clock cycle will power  
down the internal circuitry to reduce the static power consump-  
tion. One cycle is required with chip enables asserted to reac-  
tivate the outputs.  
Counter enable inputs are provided to stall the operation of the  
address input and utilize the internal address generated by the  
internal counter for fast interleaved memory applications. A  
port’s burst counter is loaded when the port’s address strobe  
(ADS) and (CNTEN) signals are LOW. When the port’s counter  
enable (CNTEN) is asserted and the ADS is deasserted, the  
address counter will increment on each LOW to HIGH transi-  
tion of that port’s clock signal. This will read/write one word  
from/into each successive address location until CNTEN is  
deasserted. The counter can address the entire memory array  
and will loop back to the start. Counter reset (CNTRST) is used  
to reset the unmasked portion of the burst counter to 0s. A  
counter-mask register is used to control the counter wrap. The  
counter and mask register operations are described in more  
detail in the following sections.  
• Separate byte enables on both ports  
• Commercial and Industrial temperature ranges  
• IEEE 1149.1 JTAG boundary scan  
• 172-ball BGA (1-mm pitch) (15 mm x 15 mm x 0.51 mm)  
New features added to the CY7C0851V25/CY7C0852V25 in-  
clude: readback of burst-counter internal address value on ad-  
dress lines, counter-mask registers to control the counter  
wrap-around and counter interrupt (CNTINT) flags, readback  
of mask register value on address lines, retransmit functional-  
ity, interrupt flags for message passing, JTAG for boundary  
scan, and asynchronous Master Reset.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 17, 2000  

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