Datasheet > 存储 > SRAM> CY7C0851V-133AC

CY7C0851V-133AC

更新时间： 2024-11-06 22:17:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
29页	764K
描述
FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C0851V-133AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
针数：	176	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	5.75
Is Samacsys：	N	最长访问时间：	4.4 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	133 MHz
I/O 类型：	COMMON	JESD-30 代码：	S-PQFP-G176
JESD-609代码：	e0	长度：	24 mm
内存密度：	2359296 bit	内存集成电路类型：	DUAL-PORT SRAM
内存宽度：	36	功能数量：	1
端口数量：	2	端子数量：	176
字数：	65536 words	字数代码：	64000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	64KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP176,1.0SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.075 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.3 mA	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	24 mm	Base Number Matches：	1

CY7C0851V-133AC 数据手册

CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K

Synchronous Dual-Port RAM

x 36 and 128K/256K x 18

CY7C0850V/CY7C0851V

CY7C0852V/CY7C0853V

FLEx36 3.3V 32K/64K/128K/256K x 36

Synchronous Dual-Port RAM

Functional Description

Features

• True dual-ported memory cells that allow simultaneous

The FLEx36 family includes 1M, 2M, 4M and 9M pipelined,

synchronous, true dual-port static RAMs that are high-speed,

low-power 3.3V CMOS. Two ports are provided, permitting

independent, simultaneous access to any location in memory.

The result of writing to the same location by more than one port

at the same time is undefined. Registers on control, address,

and data lines allow for minimal set-up and hold time.

During a Read operation, data is registered for decreased

cycle time. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally (more details to follow). The internal Write pulse width is

independent of the duration of the R/W input signal. The

internal Write pulse is self-timed to allow the shortest possible

cycle times.

access of the same memory location

• Synchronous pipelined operation

• Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit

devices

• Pipelined output mode allows fast operation

• 0.18-micron CMOS for optimum speed and power

• High-speed clock to data access

• 3.3V low power

—Active as low as 225 mA (typ)

— Standby as low as 55 mA (typ)

• Mailbox function for message passing

• Global master reset

• Separate byte enables on both ports

• Commercial and industrial temperature ranges

• IEEE 1149.1-compatible JTAG boundary scan

• 172-ball FBGA (1 mm pitch) (15 mm × 15 mm)

• 176-pin TQFP (24 mm × 24 mm × 1.4 mm)

• Counter wrap around control

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle with chip enables asserted is required

to reactivate the outputs.

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

— Internal mask register controls counter wrap-around

— Counter-interrupt flags to indicate wrap-around

— Memory block retransmit operation

• Counter readback on address lines

• Mask register readback on address lines

The CY7C0853 device in this family has limited features.

Please see See “Address Counter and Mask Register

Operations^[10]” on page 8. for details.

• Dual Chip Enables on both ports for easy depth

expansion

Table 1. Product Selection Guide

Density

1-Mbit

2-Mbit

4-Mbit

9-Mbit

(32K x 36)

CY7C0850V

167

(64K x 36)

(128K x 36)

(256K x 36)

CY7C0851V

CY7C0852V

CY7C0853V

133

Part Number

Max. Speed (MHz)

Max. Access Time - clock to Data (ns)

Typical operating current (mA)

Package

167

4.0

167

4.0

4.7

225

270

176TQFP

172FBGA

176TQFP

172FBGA

176TQFP

172FBGA

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-06070 Rev. *D

Revised June 24, 2004

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C0851V-133AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C0851V-133ACT	CYPRESS	获取价格	暂无描述
CY7C0851V-133AI	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851V-133BBC	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851V-133BBI	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851V-150AC	CYPRESS	获取价格	Dual-Port SRAM, 64KX36, 4ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
CY7C0851V-150BBC	ROCHESTER	获取价格	64KX36 DUAL-PORT SRAM, 4ns, PBGA172, 15 X 15 MM, 1 MM PITCH, BGA-172
CY7C0851V-167AC	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851V-167BBC	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851V25	CYPRESS	获取价格	SRAM
CY7C0852AV	CYPRESS	获取价格	FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

与CY7C0851V-133AC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

16
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C0851V-133AC

CY7C0851V-133AC 技术参数

CY7C0851V-133AC 数据手册

与CY7C0851V-133AC相关器件

与CY7C0851V-133AC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C0851V-133AC

CY7C0851V-133AC 技术参数

CY7C0851V-133AC 数据手册

与CY7C0851V-133AC相关器件

与CY7C0851V-133AC相关文章

您还可以找

您在本页遇到什么问题？