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CY7C0430V

更新时间: 2024-11-07 00:01:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
37页 908K
描述
3.3V 64K x 18 Synchronous QuadPort⑩ Static RAM

CY7C0430V 数据手册

 浏览型号CY7C0430V的Datasheet PDF文件第2页浏览型号CY7C0430V的Datasheet PDF文件第3页浏览型号CY7C0430V的Datasheet PDF文件第4页浏览型号CY7C0430V的Datasheet PDF文件第5页浏览型号CY7C0430V的Datasheet PDF文件第6页浏览型号CY7C0430V的Datasheet PDF文件第7页 
30V  
PRELIMINARY  
CY7C0430V  
3.3V 64K x 18  
Synchronous QuadPort™ Static RAM  
• Counter wrap-around control  
Features  
— Internal mask register controls counter wrap-around  
• True four-ported memory cells which allow simulta-  
neous access of the same memory location  
• Synchronous Pipelined device  
— Counter-Interrupt flags to indicate wrap-around  
• Counter readback on address lines  
• Mask register readback on address lines  
• Interrupt flags for message passing  
— 64K x 18 organization  
• Pipelined output mode allows fast 133-MHz operation  
• High Bandwidth up to 10 Gbps (133 MHz x 18 bits wide  
x 4 ports)  
• 0.25-micron CMOS for optimum speed/power  
• High-speed clock to data access 4.7 ns (max.)  
• 3.3V Low operating power  
• Master reset for all ports  
• Width and depth expansion capabilities  
• DualChipEnablesonallportsforeasydepthexpansion  
• Separate upper-byte and lower-byte controls on all  
ports  
— Active = 750mA (maximum)  
• 272-BGA package (27 mm x 27 mm 1.27 mm ball pitch)  
• Commercial and Industrial temperature ranges  
• IEEE 1149.1 JTAG boundary scan  
— Standby = 1mA (maximum)  
• BIST (Built In Self Test) controller  
Top Level Logic Block Diagram  
Port 1 Operation-Control Logic Blocks[1]  
Reset  
MRST  
Logic  
UB  
P1  
LB  
R/W  
OE  
P1  
Port-1  
Control  
Logic  
P1  
P1  
TMS  
JTAG  
TCK  
Controller  
TDO  
CE  
CE  
TDI  
0P1  
1P1  
CLKBIST  
BIST  
CLK  
P1  
18  
Port 1  
I/O  
Port 4 Logic Blocks[2]  
I/O - I/O  
0P1  
17P1  
CLK  
P1  
16  
A
–A  
0P1  
15P1  
Port 1  
Port 2  
Port 4  
Port 1  
MKLD  
CNTLD  
P1  
Counter/  
Mask Reg/  
Address  
P1  
CNTINC  
CNTRD  
P1  
RAM  
Array  
P1  
MKRD  
Decode  
P1  
P1  
P1  
CNTRST  
INT  
CNTINT  
Port 3  
P1  
Port 2 Logic Blocks[2]  
Port 3 Logic Blocks[2]  
Notes:  
1. Port 1 Control Logic Block is detailed on page 2.  
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134  
408-943-2600  
November 18, 1999  

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