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CY7C0251V-25AI PDF预览

CY7C0251V-25AI

更新时间: 2024-09-18 14:48:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
18页 296K
描述
Dual-Port SRAM, 8KX18, 25ns, CMOS, PQFP100, PLASTIC, TQFP-100

CY7C0251V-25AI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-100
针数:100Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.84最长访问时间:25 ns
其他特性:INTERRUPT FLAGI/O 类型:COMMON
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:147456 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
功能数量:1端口数量:2
端子数量:100字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8KX18输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0001 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.185 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

CY7C0251V-25AI 数据手册

 浏览型号CY7C0251V-25AI的Datasheet PDF文件第2页浏览型号CY7C0251V-25AI的Datasheet PDF文件第3页浏览型号CY7C0251V-25AI的Datasheet PDF文件第4页浏览型号CY7C0251V-25AI的Datasheet PDF文件第5页浏览型号CY7C0251V-25AI的Datasheet PDF文件第6页浏览型号CY7C0251V-25AI的Datasheet PDF文件第7页 
51  
CY7C024V/025V/026V  
PRELIMINARY  
CY7C0241V/0251V/036V  
3.3V 4K/8K/16K x 16/18  
Dual-Port Static RAM  
• Automatic power-down  
Features  
• Expandable data bus to 32/36 bits or more using Mas-  
ter/Slave chip select when using more than one device  
• On-chip arbitration logic  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
• 4/8/16K x 16 organization (CY7C024V/025V/026V)  
• 4/8K x 18 organization (CY7C0241V/0251V)  
• 16K x 18 organization (CY7C036V)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 15/25 ns  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Separate upper-byte and lower-byte control  
• Pin select for Master or Slave  
• Low operating power  
• Commercial and industrial temperature ranges  
• Available in 100-pin TQFP  
Active: I = 115 mA (typical)  
CC  
• Pin-compatible and functionally equivalent to  
IDT70V24, 70V25, and 7V0261.  
— Standby: I  
= 10 A (typical)  
µ
SB3  
• Fully asynchronous operation  
Logic Block Diagram  
R/W  
R/W  
UB  
L
R
R
UB  
L
CE  
CE  
LB  
L
R
R
LB  
L
OE  
OE  
R
L
8/9  
8/9  
8/9  
8/9  
[1]  
[1]  
I/O  
–I/O  
I/O  
–I/O  
8/9L  
8/9L  
15/17L  
15/17R  
[2]  
I/O –I/O  
[2]  
I/O  
Control  
I/O  
Control  
I/O –I/O  
0L  
7/8L  
0L  
7/8R  
12/13/14  
12/13/14  
[3]  
[3]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A
A
–A  
A
A
–A  
11/12/13R  
0L  
0L  
11/1213L  
0R  
0R  
RAM Array  
12/13/14  
12/13/14  
–A[3]  
–A[3]  
11/12/13R  
11/12/13L  
CE  
CE  
OE  
Interrupt  
Semaphore  
Arbitration  
L
R
R
OE  
L
R/W  
R/W  
SEM  
L
R
R
SEM  
L
[4]  
[4]  
BUSY  
BUSY  
INT  
UB  
L
R
R
R
R
INT  
L
UB  
L
LB  
M/S  
LB  
L
Notes:  
1. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices  
2. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.  
3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.  
4. BUSY is an output in master mode and an input in slave mode.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
November 7, 1997- Revised March 2, 1998  

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