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CY7C025-55JXC PDF预览

CY7C025-55JXC

更新时间： 2024-11-07 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
21页 524K
描述
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY

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CY7C025-55JXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：LCC包装说明：LEAD FREE, PLASTIC, LCC-84
针数：84Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.27Is Samacsys：N
最长访问时间：55 nsI/O 类型：COMMON
JESD-30 代码：S-PQCC-J84JESD-609代码：e3
长度：29.3116 mm内存密度：131072 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端口数量：2端子数量：84
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC84,1.2SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：5.08 mm最大待机电流：0.015 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.23 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：29.3116 mmBase Number Matches：1

CY7C025-55JXC 数据手册

 浏览型号CY7C025-55JXC的Datasheet PDF文件第2页浏览型号CY7C025-55JXC的Datasheet PDF文件第3页浏览型号CY7C025-55JXC的Datasheet PDF文件第4页浏览型号CY7C025-55JXC的Datasheet PDF文件第5页浏览型号CY7C025-55JXC的Datasheet PDF文件第6页浏览型号CY7C025-55JXC的Datasheet PDF文件第7页 
CY7C024/0241  
CY7C025/0251  
4K x 16/18 and 8K x 16/18 Dual-Port  
Static RAM with SEM, INT, BUSY  
Functional Description  
Features  
• True Dual-Ported memory cells which allow simulta-  
The CY7C024/0241 and CY7C025/0251 are low-power  
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs.  
Various arbitration schemes are included on the CY7C024/  
0241 and CY7C025/0251 to handle situations when multiple  
processors access the same piece of data. Two ports are  
provided, permitting independent, asynchronous access for  
reads and writes to any location in memory. The CY7C024/  
0241 and CY7C025/0251 can be utilized as standalone  
16-/18-bit dual-port static RAMs or multiple devices can be  
combined in order to function as a 32-/36-bit or wider master/  
slave dual-port static RAM. An M/S pin is provided for imple-  
menting 32-/36-bit or wider memory applications without the  
need for separate master and slave devices or additional  
discrete logic. Application areas include interprocessor/multi-  
processor designs, communications status buffering, and  
dual-port video/graphics memory.  
Each port has independent control pins: Chip Enable (CE),  
Read or Write Enable (R/W), and Output Enable (OE). Two  
flags are provided on each port (BUSY and INT). BUSY  
signals that the port is trying to access the same location  
currently being accessed by the other port. The Interrupt Flag  
(INT) permits communication between ports or systems by  
means of a mail box. The semaphores are used to pass a flag,  
or token, from one port to the other to indicate that a shared  
resource is in use. The semaphore logic is comprised of eight  
shared latches. Only one side can control the latch  
(semaphore) at any time. Control of a semaphore indicates  
that a shared resource is in use. An automatic power-down  
feature is controlled independently on each port by a chip  
select (CE) pin.  
neous reads of the same memory location  
• 4K x 16 organization (CY7C024)  
• 4K x 18 organization (CY7C0241)  
• 8K x 16 organization (CY7C025)  
• 8K x 18 organization (CY7C0251)  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
• Low operating power: ICC = 150 mA (typ.)  
• Fully asynchronous operation  
• Automatic power-down  
• Expandable data bus to 32/36 bits or more using  
Master/Slave chip select when using more than one  
device  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Separate upper-byte and lower-byte control  
• Pin select for Master or Slave  
• Available in 84-pin Lead (Pb)-free PLCC, 84-pin PLCC,  
100-pin Lead (Pb)-free TQFP, and 100-pin TQFP  
The CY7C024/0241 and CY7C025/0251 are available in  
84-pin Lead (Pb)-free PLCCs, 84-pin PLCCs (CY7C024 and  
CY7C025 only), 100-pin Lead (Pb)-free Thin Quad Plastic  
Flatplack (TQFP) and 100-pin Thin Quad Plastic Flatpack.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-06035 Rev. *C  
Revised November 11, 2004  
1234567...21

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与CY7C025-55JXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C025-55JXI CYPRESS

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 		4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C025AV CYPRESS

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 		3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
CY7C025AV-20AC CYPRESS

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 		3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
CY7C025AV-20AXC CYPRESS

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 		3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
CY7C025AV-20AXI CYPRESS

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 		3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
CY7C025AV-25AC CYPRESS

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 		3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
CY7C025AV-25AI ROCHESTER

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 		8KX16 DUAL-PORT SRAM, 25ns, PQFP100, PLASTIC, TQFP-100
CY7C025AV-25AI CYPRESS

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 		3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
CY7C025AV-25AIT ROCHESTER

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 		8KX16 DUAL-PORT SRAM, 25ns, PQFP100, PLASTIC, TQFP-100
CY7C025AV-25AIT CYPRESS

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 		Dual-Port SRAM, 8KX16, 25ns, CMOS, PQFP100, PLASTIC, TQFP-100

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