Datasheet > CY7B9920

CY7B9920

更新时间： 2024-09-29 23:16:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
7页	165K
描述
Low Skew Clock Buffer

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7B9920 数据手册

1CY7B9920

fax id: 3516

CY7B9910

CY7B9920

Low Skew

Clock Buffer

Features

Block Diagram Description

• All outputs skew <100 ps typical (250 max.)

• 15- to 80-MHz output operation

• Zero input to output delay

• 50% duty-cycle outputs

• Outputs drive 50Ω terminated lines

• Low operating current

Phase Frequency Detector and Filter

These two blocks accept inputs from the reference frequency

(REF) input and the feedback (FB) input and generate correc-

tion information to control the frequency of the Voltage-Con-

trolled Oscillator (VCO). These blocks, along with the VCO,

form a Phase-Locked Loop (PLL) that tracks the incoming

REF signal.

• 24-pin SOIC package

VCO

• Jitter: <200 ps peak to peak, <25 ps RMS

• Compatible with Pentium™-based processors

The VCO accepts analog control inputs from the PLL filter

block and generates a frequency. The operational range of the

VCO is determined by the FS control pin.

Functional Description

The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer

low-skew system clock distribution. These multiple-output

clock drivers optimize the timing of high-performance comput-

er systems. Eight individual drivers can each drive terminated

transmission lines with impedances as low as 50Ω while deliv-

ering minimal and specified output skews and full-swing logic

levels (CY7B9910 TTL or CY7B9920 CMOS).

Test Mode

The TEST input is a three-level input. In normal system oper-

ation, this pin is connected to ground, allowing the

CY7B9910/CY7B9920 to operate as explained above. (For

testing purposes, any of the three-level inputs can have a re-

movable jumper to ground, or be tied LOW through a 100Ω

resistor. This will allow an external tester to change the state of

these pins.)

The completely integrated PLL allows “zero delay” capability.

External divide capability, combined with the internal PLL, allows

distribution of a low-frequency clock that can be multiplied by virtu-

ally any factor at the clock destination. This facility minimizes clock

distribution difficulty while allowing maximum system clock speed

and flexibility.

If the TEST input is forced to its MID or HIGH state, the device

will operate with its internal phase-locked loop disconnected,

and input levels supplied to REF will directly control all outputs.

Relative output to output functions are the same as in normal

mode.

Logic Block Diagram

Pin Configuration

TEST

Voltage

Controlled

Oscillator

PHASE

FREQ

DET

FILTER

REF

SOIC

Top View

REF

GND

TEST

CCQ

GND

CCQ

CCN

7B9910

7B9920

GND

CCN

7B9910–1

7B9910–2

Pentium is a trademark of Intel Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

November 1994 – Revised July 7, 1997

12 3 4 5 6 7

中文翻译

下载PDF

与CY7B9920相关器件

型号	品牌	获取价格	描述	数据表
CY7B9920-2SC	CYPRESS	获取价格	Low Skew Clock Buffer
CY7B9920-2SC[20]	CYPRESS	获取价格	Low Skew Clock Buffer
CY7B9920-2SCT	CYPRESS	获取价格	暂无描述
CY7B9920-5SC	CYPRESS	获取价格	Low Skew Clock Buffer
CY7B9920-5SCT	CYPRESS	获取价格	Low Skew Clock Buffer
CY7B9920-5SCT	ROCHESTER	获取价格	7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 0.300 I
CY7B9920-5SI	CYPRESS	获取价格	Low Skew Clock Buffer
CY7B9920-7SC	CYPRESS	获取价格	Low Skew Clock Buffer
CY7B9920-7SC[20]	CYPRESS	获取价格	Low Skew Clock Buffer
CY7B9920-7SCT	CYPRESS	获取价格	PLL Based Clock Driver, 7B Series, 8 True Output(s), 0 Inverted Output(s), BICMOS, PDSO24,

与CY7B9920相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

29
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

23
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

25
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

35

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7B9920

CY7B9920 数据手册

与CY7B9920相关器件

与CY7B9920相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7B9920

CY7B9920 数据手册

与CY7B9920相关器件

与CY7B9920相关文章

您还可以找

您在本页遇到什么问题？