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CY74FCT841ATSOCR PDF预览

CY74FCT841ATSOCR

更新时间: 2024-09-15 12:59:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 86K
描述
FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, SOIC-24

CY74FCT841ATSOCR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.13系列:FCT
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:15.4 mm逻辑集成电路类型:BUS DRIVER
位数:10功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):16 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

CY74FCT841ATSOCR 数据手册

 浏览型号CY74FCT841ATSOCR的Datasheet PDF文件第2页浏览型号CY74FCT841ATSOCR的Datasheet PDF文件第3页浏览型号CY74FCT841ATSOCR的Datasheet PDF文件第4页浏览型号CY74FCT841ATSOCR的Datasheet PDF文件第5页浏览型号CY74FCT841ATSOCR的Datasheet PDF文件第6页浏览型号CY74FCT841ATSOCR的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY54/74FCT841T  
SCCS035 - September 1994 - Revised March 2000  
10-Bit Latch  
High-speed parallel latches  
Buffered common latch enable input  
Features  
• Function, pinout, and drive compatible with FCT, F, and  
AM29841 logic  
• FCT-C speed at 5.5 ns max. (Com’l)  
FCT-B speed at 6.5 ns max. (Com’l)  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
Functional Description  
The FCT841T bus interface latch is designed to eliminate the  
extra packages required to buffer existing latches and provide  
extra data width for wider address/data paths or buses  
carrying parity. The FCT841T is a buffered 10-bit wide version  
of the FCT373 function.  
The FCT841T high-performance interface is designed for  
high-capacitance load drive capability while providing  
low-capacitance bus loading at both inputs and outputs.  
Outputs are designed for low-capacitance bus loading in the  
high impedance state and are designed with a power-off  
disable feature to allow for live insertion of boards.  
• Power-off disable feature  
Matched rise and fall times  
ESD > 2000V  
• Fully compatible with TTL input and output logic levels  
Sink current  
64 mA (Com’l),  
32 mA (Mil)  
Source current 32 mA (Com’l),  
12 mA (Mil)  
Functional Block Diagram  
D
0
D
1
D
2
D
D
4
D
D
D
N
3
5
N- 1  
D
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
Q
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
OE  
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
N- 1  
Y
N
Logic Block Diagram  
Pin Configurations  
DIP/QSOP/SOIC  
Top View  
10  
D
D
10  
Q
Y
24  
23  
22  
21  
OE  
1
2
3
4
LE  
V
CC  
LE  
D
0
Y
0
Y
1
D
1
OE  
Y
2
D
2
Y
20  
19  
18  
17  
16  
D
3
5
3
D
4
Y
4
6
D
5
Y
5
7
Y
6
D
6
8
D
7
9
Y
7
Y
D
8
10  
11  
8
15  
14  
13  
Y
9
D
9
LE  
GND  
12  
Copyright © 2000, Texas Instruments Incorporated  

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