CY74FCT821BTSOCR

更新时间： 2024-02-23 14:00:28

品牌	Logo	应用领域
德州仪器 - TI		总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数	文件大小	规格书
10页	88K
描述
暂无描述

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY74FCT821BTSOCR 数据手册

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY74FCT821T

CY74FCT823T

CY74FCT825T

SCCS033 - May 1994 - Revised March 2000

8-/9-/10-Bit Bus Interface Registers

Features

Functional Description

• Function, pinout, and drive compatible with FCT, F, and

Am29821/23/25 logic

• FCT-C speed at 6.0 ns max.

FCT-B speed at 7.5 ns max.

• Reduced V_OH(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

These bus interface registers are designed to eliminate the

extra packages required to buffer existing registers and

provide extra data width for wider address/data paths or buses

carrying parity. The FCT821T is a buffered, 10-bit wide version

of the popular FCT374 function. The FCT823T is a 9-bit wide

buffered register with clock enable (EN) and clear (CLR) ideal

for parity bus interfacing in high-performance micropro-

grammed systems. The FCT825T is an 8-bit buffered register

with all the FCT823T controls plus multiple enables (OE₁,

OE₂, OE₃) to allow multiuser control of the interface, e.g., CS,

DMA, and RD/WR. They are ideal for use as an output port

• Power-off disable feature

• Matched rise and fall times

• Fully compatible with TTL input and output logic levels

• ESD > 2000V

requiring high I_OL/I_OH

These devices are designed for high-capacitance load drive

capability, while providing low-capacitance bus loading at both

inputs and outputs. Outputs are designed for low-capacitance

bus loading in the high-impedance state and are designed with

a power-off disable feature to allow for live insertion of boards.

• Sink current

Source current

64 mA

32 mA

• High-speed parallel registers with positive

edge-triggered D-type ﬂip-ﬂops

• Bufferedcommonclockenable(EN)andasynchronous

clear input (CLR)

• Extended commercial range of −40˚C to +85˚C

Logic Block Diagram

N- 1

[1]

CLR

Note:

1. Not on FCT821.

12 3 4 5 6 7...10

中文翻译

下载PDF

与CY74FCT821BTSOCR相关器件

型号	品牌	获取价格	描述	数据表
CY74FCT821BTSOCT	TI	获取价格	8-/9-/10-Bit Bus Interface Registers
CY74FCT821BTSOCT	CYPRESS	获取价格	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, 0.300 INCH, PLASTIC, SO
CY74FCT821BTSOCTE4	TI	获取价格	10-Bit Bus Interface Flip-Flops with 3-State Outputs 24-SOIC -40 to 85
CY74FCT821BTSOCTG4	TI	获取价格	10-Bit Bus Interface Flip-Flops with 3-State Outputs 24-SOIC -40 to 85
CY74FCT821CTQCT	TI	获取价格	8-/9-/10-Bit Bus Interface Registers
CY74FCT821CTQCTE4	TI	获取价格	FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, QSOP-24
CY74FCT821CTSOC	TI	获取价格	8-/9-/10-Bit Bus Interface Registers
CY74FCT821CTSOC	CYPRESS	获取价格	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, 0.300 INCH, PLASTIC, SO
CY74FCT821CTSOCG4	TI	获取价格	FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
CY74FCT821CTSOCR	TI	获取价格	FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24

与CY74FCT821BTSOCR相关文章

采用MCU+MPU双处理器架构实现的创新应用设计探索
2024-08-23

5
解读L9904TR手册资料：产品概述、主要功能、电气参数
2024-08-20

19
芯片底部填充工艺：提升电子设备可靠性的关键步骤
2024-08-14

83
REF03GPZ资料解读：主要特征、技术参数、应用场景
2024-08-05

142

产品中心

服务支持

精选活动

关于我们

帮助中心

CY74FCT821BTSOCR

CY74FCT821BTSOCR 数据手册

与CY74FCT821BTSOCR相关器件

与CY74FCT821BTSOCR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY74FCT821BTSOCR

CY74FCT821BTSOCR 数据手册

与CY74FCT821BTSOCR相关器件

与CY74FCT821BTSOCR相关文章

您还可以找

您在本页遇到什么问题？