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CY74FCT821BTSOCR PDF预览

CY74FCT821BTSOCR

更新时间: 2024-11-21 13:07:11
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德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
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10页 88K
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CY74FCT821BTSOCR 数据手册

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Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT821T  
CY74FCT823T  
CY74FCT825T  
SCCS033 - May 1994 - Revised March 2000  
8-/9-/10-Bit Bus Interface Registers  
Features  
Functional Description  
• Function, pinout, and drive compatible with FCT, F, and  
Am29821/23/25 logic  
• FCT-C speed at 6.0 ns max.  
FCT-B speed at 7.5 ns max.  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
These bus interface registers are designed to eliminate the  
extra packages required to buffer existing registers and  
provide extra data width for wider address/data paths or buses  
carrying parity. The FCT821T is a buffered, 10-bit wide version  
of the popular FCT374 function. The FCT823T is a 9-bit wide  
buffered register with clock enable (EN) and clear (CLR) ideal  
for parity bus interfacing in high-performance micropro-  
grammed systems. The FCT825T is an 8-bit buffered register  
with all the FCT823T controls plus multiple enables (OE1,  
OE2, OE3) to allow multiuser control of the interface, e.g., CS,  
DMA, and RD/WR. They are ideal for use as an output port  
• Power-off disable feature  
• Matched rise and fall times  
• Fully compatible with TTL input and output logic levels  
• ESD > 2000V  
requiring high IOL/IOH  
.
These devices are designed for high-capacitance load drive  
capability, while providing low-capacitance bus loading at both  
inputs and outputs. Outputs are designed for low-capacitance  
bus loading in the high-impedance state and are designed with  
a power-off disable feature to allow for live insertion of boards.  
• Sink current  
Source current  
64 mA  
32 mA  
• High-speed parallel registers with positive  
edge-triggered D-type flip-flops  
• Bufferedcommonclockenable(EN)andasynchronous  
clear input (CLR)  
• Extended commercial range of 40˚C to +85˚C  
Logic Block Diagram  
D
0
D
D
4
D
5
D
D
3
D
N- 1  
D
N
1
2
[1]  
EN  
[1]  
CLR  
CL  
CL  
CL  
CL  
CL  
CL  
CL  
CL  
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
CP  
CP  
CP  
CP  
CP  
CP  
CP  
CP  
Q
CP  
OE  
Y
0
Y
1
Y
4
Y
5
Y
2
Y
3
Y
n-  
Y
n
1
Note:  
1. Not on FCT821.  
Copyright © 2000, Texas Instruments Incorporated  

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