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CY74FCT821ATSOCTE4 PDF预览

CY74FCT821ATSOCTE4

更新时间： 2023-07-15 00:00:00
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件
页数 文件大小 规格书
16页 686K
描述
FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24

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CY74FCT821ATSOCTE4 数据手册

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CY74FCT821T  
10-BIT BUS-INTERFACE REGISTER  
WITH 3-STATE OUTPUTS  
SCCS033B– MAY 1994 – REVISED NOVEMBER 2001  
P, Q, OR SO PACKAGE  
(TOP VIEW)  
Function, Pinout, and Drive Compatible  
With FCT, F Logic, and AM29821  
Reduced V  
Equivalent FCT Functions  
(Typically = 3.3 V) Version of  
OH  
OE  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
CC  
0
D
D
D
D
D
D
D
D
D
D
2
0
1
2
3
4
5
6
7
8
9
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
3
1
4
2
5
3
6
I
Supports Partial-Power-Down Mode  
4
off  
7
Operation  
5
8
6
Matched Rise and Fall Times  
9
7
Fully Compatible With TTL Input and  
Output Logic Levels  
10  
11  
8
9
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
GND 12  
13 CP  
– 1000-V Charged-Device Model (C101)  
64-mA Output Sink Current  
32-mA Output Source Current  
High-Speed Parallel Register With  
Positive-Edge-Triggered D-Type Flip-Flops  
3-State Outputs  
description  
This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and  
provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT821T is a  
10-bit-wide buffered version of the popular CY74FCT374 function. This device is ideal for use as an output port  
requiring high I /I  
.
OL OH  
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading  
at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
PIN DESCRIPTION  
NAME  
D
I/O  
I
DESCRIPTION  
D flip-flop data inputs  
CP  
Y
O
O
Clock pulse for the register. Enters data into the register on the low-to-high clock transition.  
Register 3-state outputs  
Output control. When OE is high, the Y outputs are in the high-impedance state.  
When OE is low, true register data is present at the Y outputs.  
I
OE  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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