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CY74FCT652CTSOCR

更新时间： 2024-10-02 13:00:47
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 65K
描述
FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24

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CY74FCT652CTSOCR 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.27Is Samacsys：N
系列：FCTJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：15.4 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：5.7 ns
认证状态：Not Qualified座面最大高度：2.65 mm
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

CY74FCT652CTSOCR 数据手册

 浏览型号CY74FCT652CTSOCR的Datasheet PDF文件第2页浏览型号CY74FCT652CTSOCR的Datasheet PDF文件第3页浏览型号CY74FCT652CTSOCR的Datasheet PDF文件第4页浏览型号CY74FCT652CTSOCR的Datasheet PDF文件第5页浏览型号CY74FCT652CTSOCR的Datasheet PDF文件第6页浏览型号CY74FCT652CTSOCR的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT652T  
SCCS032 - September 1994 - Revised March 2000  
8-Bit Registered Transceiver  
Features  
Functional Description  
• Function, pinout, and drive compatible with FCT and  
F logic  
• FCT-C speed at 5.4 ns max. (Com’l)  
FCT-A speed at 6.3 ns max. (Com’l)  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
The FCT652T consists of bus transceiver circuits, D-type  
flip-flops, and control circuitry arranged for multiplexed  
transmission of data directly from the input bus or from the  
internal storage registers. GAB and GBA control pins are  
provided to control the transceiver functions. SAB and SBA  
control pins are provided to select either real-time or stored  
data transfer. The circuitry used for select control will eliminate  
the typical decoding glitch that occurs in a multiplexer during  
the transition between stored and real-time data. A LOW input  
level selects real-time data and a HIGH selects stored data.  
• Power-off disable feature  
• Matched rise and fall times  
Data on the A or B data bus, or both, can be stored in the  
internal D flip-flops by LOW-to-HIGH transitions at the  
appropriate clock pins (CPAB or CPBA), regardless of the  
select or enable control pins. When SAB and SBA are in the  
real-time transfer mode, it is also possible to store data without  
using the internal D-type flip-flops by simultaneously enabling  
GAB and GBA. In this configuration, each output reinforces its  
input. Thus, when all other data sources to the two sets of bus  
lines are at high impedance, each set of bus lines will remain  
at its last state.  
• Fully compatible with TTL input and output logic levels  
• Sink Current  
Source Current  
64mA  
32mA  
• Independent register for A and B buses  
• Multiplexed real-time and stored data transfer  
• Extended commercial range of −40˚C to +85˚C  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
Logic Block Diagram  
Pin Configurations  
CPBA  
GAB  
LCC  
Top View  
SBA  
SAB  
11 10 9  
8 7 6 5  
12  
13  
14  
15  
16  
4
A
GAB  
7
A
GBA  
3
2
1
28  
27  
26  
SAB  
CPAB  
NC  
8
GND  
NC  
CPAB  
V
CC  
B
8
B
B
B REG  
17  
18  
CPBA  
SBA  
7
6
1 OF 8 CHANNELS  
19 20 21 22 2324 25  
D
C
SOIC/QSOP  
Top View  
A
1
A REG  
B
1
CPAB  
SAB  
V
CC  
1
2
3
4
24  
23  
22  
21  
D
CPBA  
SBA  
GAB  
C
A
1
GBA  
A
2
B
1
5
6
7
8
9
20  
19  
18  
17  
16  
A
3
B
2
A
4
B
3
A
5
B
4
A
6
B
5
A
7
B
6
10  
11  
15  
14  
A
8
B
7
TO 7 OTHERCHANNELS  
GND  
B
8
12  
13  
Copyright © 2000, Texas Instruments Incorporated  
1234567

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