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CY74FCT573TSOC PDF预览

CY74FCT573TSOC

更新时间: 2024-11-21 05:18:59
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 83K
描述
8-Bit Latches

CY74FCT573TSOC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.23
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:FCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):0.2 mAProp。Delay @ Nom-Sup:8 ns
传播延迟(tpd):13 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

CY74FCT573TSOC 数据手册

 浏览型号CY74FCT573TSOC的Datasheet PDF文件第2页浏览型号CY74FCT573TSOC的Datasheet PDF文件第3页浏览型号CY74FCT573TSOC的Datasheet PDF文件第4页浏览型号CY74FCT573TSOC的Datasheet PDF文件第5页浏览型号CY74FCT573TSOC的Datasheet PDF文件第6页浏览型号CY74FCT573TSOC的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY54/74FCT373T  
CY54/74FCT573T  
SCCS021 - May 1994 - Revised February 2000  
8-Bit Latches  
Features  
Functional Description  
• Function and pinout compatible with FCT, and F logic  
• FCT-C speed at 4.2 ns max. (Com’l),  
FCT-A speed at 5.2 ns max. (Com’l)  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature  
• ESD > 2000V  
• Matched rise and fall times  
• Extended commercial range of 40˚C to +85˚C  
• Fully compatible with TTL input and output logic levels  
The FCT373T and FCT573T consist of eight latches with  
three-state outputs for bus organized applications. When latch  
enable (LE) is HIGH, the flip-flops appear transparent to the  
data. Data that meets the required set-up times are latched  
when LE transitions from HIGH to LOW. Data appears on the  
bus when the (OE) is LOW. When output enable is HIGH, the  
bus output is in the impedance state. In this mode, data may  
be entered into the latches. The FCT573T is identical to the  
FCT373T except for the flow-through pinout, which simplifies  
board design.  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
• Sink current  
64 mA (Com’l), 32 mA (Mil)  
Source current 32 mA (Com’l), 12 mA (Mil)  
Logic Block Diagram  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE  
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
OE  
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Pin Configurations  
DIP/SOIC/QSOP  
Top View  
DIP/SOIC/QSOP  
Top View  
OE  
1
2
3
4
5
6
7
8
9
10  
V
OE  
20  
19  
18  
17  
CC  
1
2
3
4
5
6
7
8
9
10  
V
20  
19  
18  
17  
CC  
D
0
O
0
O
0
O
7
D
1
O
1
D
0
D
7
D
2
O
2
D
1
D
6
FCT573T  
D
3
FCT373T  
O
3
16  
O
1
O
6
16  
D
4
O
4
15  
14  
13  
12  
11  
O
2
O
5
15  
14  
13  
12  
11  
D
5
O
5
D
2
D
5
D
6
O
6
D
3
D
4
D
7
O
7
O
3
O
4
GND  
LE  
GND  
LE  
Logic Symbol  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE  
OE  
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Copyright © 2000, Texas Instruments Incorporated  

CY74FCT573TSOC 替代型号

型号 品牌 替代类型 描述 数据表
CY74FCT573CTSOC TI

完全替代

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