Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT373T
CY54/74FCT573T
SCCS021 - May 1994 - Revised February 2000
8-Bit Latches
Features
Functional Description
• Function and pinout compatible with FCT, and F logic
• FCT-C speed at 4.2 ns max. (Com’l),
FCT-A speed at 5.2 ns max. (Com’l)
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• ESD > 2000V
• Matched rise and fall times
• Extended commercial range of −40˚C to +85˚C
• Fully compatible with TTL input and output logic levels
The FCT373T and FCT573T consist of eight latches with
three-state outputs for bus organized applications. When latch
enable (LE) is HIGH, the flip-flops appear transparent to the
data. Data that meets the required set-up times are latched
when LE transitions from HIGH to LOW. Data appears on the
bus when the (OE) is LOW. When output enable is HIGH, the
bus output is in the impedance state. In this mode, data may
be entered into the latches. The FCT573T is identical to the
FCT373T except for the flow-through pinout, which simplifies
board design.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
• Sink current
64 mA (Com’l), 32 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)
Logic Block Diagram
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Pin Configurations
DIP/SOIC/QSOP
Top View
DIP/SOIC/QSOP
Top View
OE
1
2
3
4
5
6
7
8
9
10
V
OE
20
19
18
17
CC
1
2
3
4
5
6
7
8
9
10
V
20
19
18
17
CC
D
0
O
0
O
0
O
7
D
1
O
1
D
0
D
7
D
2
O
2
D
1
D
6
FCT573T
D
3
FCT373T
O
3
16
O
1
O
6
16
D
4
O
4
15
14
13
12
11
O
2
O
5
15
14
13
12
11
D
5
O
5
D
2
D
5
D
6
O
6
D
3
D
4
D
7
O
7
O
3
O
4
GND
LE
GND
LE
Logic Symbol
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Copyright © 2000, Texas Instruments Incorporated