Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT543T
SCCS030 - May 1994 - Revised March 2000
8-Bit Latched Registered Transceiver
Features
Functional Description
• Function, pinout, and drive compatible with FCT and
The FCT543T octal latched transceiver contains two sets of
eight D-type latches with separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) controls for each set to
permit independent control of inputting and outputting in either
direction of data flow. For data flow from A to B, for example,
the A-to-B enable (CEAB) input must be LOW in order to enter
data from A or to take data from B, as indicated in the truth
table. With CEAB LOW, a LOW signal on the A-to-B latch
enable (LEAB) input makes the A-to-B latches transparent; a
subsequent LOW-to-HIGH transition of the LEAB signal puts
the A latches in the storage mode and their output no longer
change with the A inputs. With CEAB and OEAB both LOW,
the three-stage B output buffers are active and reflect the data
present at the output of the A latches. Control of data from B
to A is similar, but uses CEAB, LEAB, and OEAB inputs.
F logic
• FCT-C speed at 5.3 ns max. (Com’l)
FCT-A speed at 6.5 ns max. (Com’l)
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Sink current
Source current
64 mA (Com’l), 48 mA (Mil)
32 mA (Com’l), 12 mA (Mil)
• Separation controls for data flow in each direction
• Back to back latches for storage
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
• Extended commercial range of −40˚C to +85˚C
Functional Block Diagram
Logic Block Diagram
DetailA
B
D Q
LE
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB
OEAB
A
0
Q D
LE
CEBA
LEAB
LEBA
OEBA
A
B
B
B
B
B
B
B
1
1
2
3
4
5
6
7
B
B
B
B
B
B
B
B
7
0
1
2
3
4
5
6
A
2
A
3
A
4
DetailA x 7
A
5
A
6
Pin Configurations
A
7
SOIC/QSOP
Top View
OEBA
OEAB
1
LEBA
OEBA
24
23
22
21
CEBA
LEBA
V
CC
2
CEBA
CEAB
LEAB
3
A
0
B
0
4
A
1
B
1
A
2
5
B
2
20
19
18
17
16
A
3
6
B
3
A
4
B
4
7
A
5
B
5
8
A
6
B
6
9
A
7
B
7
10
11
12
15
14
13
CEAB
GND
LEAB
OEAB
Copyright © 2000, Texas Instruments Incorporated