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CY74FCT543CTSOC PDF预览

CY74FCT543CTSOC

更新时间： 2024-10-01 05:18:59
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 76K
描述
8-Bit Latched Registered Transceiver

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CY74FCT543CTSOC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP24,.4针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.24控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：FCT
JESD-30 代码：R-PDSO-G24长度：15.4 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.064 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：5.3 ns传播延迟（tpd）：7 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：7.5 mmBase Number Matches：1

CY74FCT543CTSOC 数据手册

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Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY54/74FCT543T  
SCCS030 - May 1994 - Revised March 2000  
8-Bit Latched Registered Transceiver  
Features  
Functional Description  
• Function, pinout, and drive compatible with FCT and  
The FCT543T octal latched transceiver contains two sets of  
eight D-type latches with separate latch enable (LEAB, LEBA)  
and output enable (OEAB, OEBA) controls for each set to  
permit independent control of inputting and outputting in either  
direction of data flow. For data flow from A to B, for example,  
the A-to-B enable (CEAB) input must be LOW in order to enter  
data from A or to take data from B, as indicated in the truth  
table. With CEAB LOW, a LOW signal on the A-to-B latch  
enable (LEAB) input makes the A-to-B latches transparent; a  
subsequent LOW-to-HIGH transition of the LEAB signal puts  
the A latches in the storage mode and their output no longer  
change with the A inputs. With CEAB and OEAB both LOW,  
the three-stage B output buffers are active and reflect the data  
present at the output of the A latches. Control of data from B  
to A is similar, but uses CEAB, LEAB, and OEAB inputs.  
F logic  
• FCT-C speed at 5.3 ns max. (Com’l)  
FCT-A speed at 6.5 ns max. (Com’l)  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature  
• Matched rise and fall times  
• Fully compatible with TTL input and output logic levels  
• ESD > 2000V  
• Sink current  
Source current  
64 mA (Com’l), 48 mA (Mil)  
32 mA (Com’l), 12 mA (Mil)  
• Separation controls for data flow in each direction  
• Back to back latches for storage  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
• Extended commercial range of −40˚C to +85˚C  
Functional Block Diagram  
Logic Block Diagram  
DetailA  
B
D Q  
LE  
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB  
OEAB  
A
0
Q D  
LE  
CEBA  
LEAB  
LEBA  
OEBA  
A
B
B
B
B
B
B
B
1
1
2
3
4
5
6
7
B
B
B
B
B
B
B
B
7
0
1
2
3
4
5
6
A
2
A
3
A
4
DetailA x 7  
A
5
A
6
Pin Configurations  
A
7
SOIC/QSOP  
Top View  
OEBA  
OEAB  
1
LEBA  
OEBA  
24  
23  
22  
21  
CEBA  
LEBA  
V
CC  
2
CEBA  
CEAB  
LEAB  
3
A
0
B
0
4
A
1
B
1
A
2
5
B
2
20  
19  
18  
17  
16  
A
3
6
B
3
A
4
B
4
7
A
5
B
5
8
A
6
B
6
9
A
7
B
7
10  
11  
12  
15  
14  
13  
CEAB  
GND  
LEAB  
OEAB  
Copyright © 2000, Texas Instruments Incorporated  
1234567...9

中文翻译

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CY74FCT543CTSOC 替代型号

型号 品牌 替代类型 描述 数据表
CY74FCT543CTSOCTG4 TI

完全替代

 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
CY74FCT543CTSOCTE4 TI

完全替代

 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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