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CY74FCT540TQC PDF预览

CY74FCT540TQC

更新时间: 2024-11-28 15:30:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 137K
描述
Bus Driver, FCT Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO20, 0.150 INCH, QSOP-20

CY74FCT540TQC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QSOP包装说明:SSOP, SSOP20,.25
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.27
其他特性:WITH DUAL OUTPUT ENABLE控制类型:ENABLE LOW
系列:FCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.064 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:5 V
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):8.5 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

CY74FCT540TQC 数据手册

 浏览型号CY74FCT540TQC的Datasheet PDF文件第2页浏览型号CY74FCT540TQC的Datasheet PDF文件第3页浏览型号CY74FCT540TQC的Datasheet PDF文件第4页浏览型号CY74FCT540TQC的Datasheet PDF文件第5页浏览型号CY74FCT540TQC的Datasheet PDF文件第6页浏览型号CY74FCT540TQC的Datasheet PDF文件第7页 
1CY54/74FCT541T  
fax id: 7002  
CY54/74FCT540T  
CY54/74FCT541T  
8-Bit Buffers/Line Drivers  
Features  
Functional Description  
Function, pinout and drive compatible with FCT and  
The FCT540T inverting buffer/line driver and the FCT541T  
non-inverting buffer/line driver are designed to be employed  
as memory address drivers, clock drivers, and bus-oriented  
transmitters/receivers. The devices provide speed and drive  
capabilities equivalent to their fastest bipolar logic  
counterparts while reducing power dissipation. The input and  
output voltage levels allow direct interface with TTL, NMOS,  
and CMOS devices without external components.  
F logic  
FCT-C speed at 4.1 ns max. (Com’l)  
FCT-A speed at 4.8 ns max. (Com’l)  
Reduced V  
(typically = 3.3V) versions of equivalent  
OH  
FCT functions  
Edge-rate control circuitry for significantly improved  
noise characteristics  
Power-off disable feature  
ESD > 2000V  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
Matched rise and fall times  
Fully compatible with TTL input and output logic levels  
• Sink current  
Source current  
64 mA (Com’l), 48 mA (Mil)  
32 mA (Com’l), 12 mA (Mil)  
Extended commercial range of 40°C to +85°C  
Pin Configurations  
Logic Block Diagram—FCT540T  
CERDIP/SOIC/QSOP  
Top View  
OE  
A
OE  
B
1
20  
19  
18  
17  
16  
OE  
V
A
CC  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
0
2
OE  
B
3
D
1
O
O
O
0
4
D
2
1
D
3
5
2
FCT540T  
D
4
6
O
15  
14  
3
4
5
6
7
D
5
O
O
O
O
7
D
6
8
13  
12  
11  
D
7
9
GND  
10  
Logic Block Diagram—FCT541T  
CERDIP/DIP/SOIC/QSOP  
Top View  
OE  
OE  
B
A
1
20  
19  
18  
17  
16  
OE  
V
CC  
A
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
0
2
3
4
5
6
OE  
B
D
1
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
2
D
3
FCT541T  
D
4
15  
14  
D
5
7
8
9
D
6
13  
12  
11  
D
7
GND  
10  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
May 1994 – Revised March 17, 1997  

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