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CY74FCT480BTPCE4

更新时间： 2024-11-25 13:47:11
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路
页数 文件大小 规格书
13页 320K
描述
Dual 8-Bit Parity Generator/Checker 24-PDIP -40 to 85

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中文翻译

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CY74FCT480BTPCE4 技术参数

是否无铅：含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：DIP
包装说明：ROHS COMPLIANT, PLASTIC, DIP-24针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.57Is Samacsys：N
系列：FCTJESD-30 代码：R-PDIP-T24
长度：31.64 mm逻辑集成电路类型：PARITY GENERATOR/CHECKER
位数：8功能数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：OPEN-DRAIN
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
传播延迟（tpd）：6.1 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Arithmetic Circuits
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

CY74FCT480BTPCE4 数据手册

 浏览型号CY74FCT480BTPCE4的Datasheet PDF文件第2页浏览型号CY74FCT480BTPCE4的Datasheet PDF文件第3页浏览型号CY74FCT480BTPCE4的Datasheet PDF文件第4页浏览型号CY74FCT480BTPCE4的Datasheet PDF文件第5页浏览型号CY74FCT480BTPCE4的Datasheet PDF文件第6页浏览型号CY74FCT480BTPCE4的Datasheet PDF文件第7页 
CY54FCT480T, CY74FCT480T  
DUAL 8-BIT PARITY GENERATORS/CHECKERS  
SCCS025B – MAY 1993 – REVISED OCTOBER 2001  
CY74FCT480T . . . P, Q, OR SO PACKAGE  
(TOP VIEW)  
Function, Pinout, and Drive Compatible  
With FCT and F Logic  
Reduced V  
of Equivalent FCT Functions  
(Typically = 3.3 V) Versions  
OH  
A
B
C
D
E
F
G
H
V
A
B
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
1
1
1
1
1
1
1
1
1
CC  
2
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
2
C
D
E
2
2
I
Supports Partial-Power-Down Mode  
2
2
off  
F
Operation  
G
H
2
Matched Rise and Fall Times  
PAR  
2
Fully Compatible With TTL Input and  
Output Logic Levels  
CHK/GEN 10  
ODD  
11  
GND 12  
15 PAR  
2
14 ERROR  
13 ODD  
1
Two 8-Bit Parity Generators/Checkers  
Open-Drain Active-Low Parity-Error Output  
Expandable for Larger Word Widths  
2
CY54FCT480T . . . L PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
4
3
2
1 28 27 26  
25  
24  
23  
22  
21  
20  
19  
C
D
E
D
E
F
NC  
G
5
1
1
1
2
2
CY54FCT480T  
– 32-mA Output Sink Current  
– 12-mA Output Source Current  
6
7
2
NC  
8
CY74FCT480T  
– 64-mA Output Sink Current  
– 32-mA Output Source Current  
F
9
1
2
H
1
PAR  
G
2
H
10  
11  
1
2
12 13 14 15 16 17 18  
description  
The ’FCT480T devices are high-speed, dual,  
8-bit parity generators/checkers. Each parity  
generator/checker accepts eight data bits and  
one parity bit as inputs, and generates a sum and  
parity-error (ERROR) output. These devices can  
be used in odd-parity systems. ERROR is an  
open-drain output designed for easy expansion of  
NC – No internal connection  
the word width by a wired-OR connection of several ’FCT480T devices. Because no additional logic is needed,  
the parity-generation or parity-checking times remain the same as for an individual ’FCT480T device.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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