5秒后页面跳转
CY74FCT399CTSOCE4 PDF预览

CY74FCT399CTSOCE4

更新时间: 2024-11-24 21:53:27
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
10页 261K
描述
Quad 2-Input Register

CY74FCT399CTSOCE4 数据手册

 浏览型号CY74FCT399CTSOCE4的Datasheet PDF文件第2页浏览型号CY74FCT399CTSOCE4的Datasheet PDF文件第3页浏览型号CY74FCT399CTSOCE4的Datasheet PDF文件第4页浏览型号CY74FCT399CTSOCE4的Datasheet PDF文件第5页浏览型号CY74FCT399CTSOCE4的Datasheet PDF文件第6页浏览型号CY74FCT399CTSOCE4的Datasheet PDF文件第7页 
CY74FCT399T  
QUAD 2-INPUT REGISTER  
SCCS024A – MARCH 1994 – REVISED OCTOBER 2001  
SO PACKAGE  
(TOP VIEW)  
Function, Pinout, and Drive Compatible  
With FCT and F Logic  
Reduced V  
Equivalent FCT Functions  
(Typically = 3.3 V) Versions of  
OH  
S
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q
Q
I
A
0A  
1A  
1B  
0B  
D
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
I
I
I
I
0D  
1D  
1C  
0C  
I
I
I
I
Supports Partial-Power-Down Mode  
off  
Operation  
Q
Q
C
CP  
B
GND  
Matched Rise and Fall Times  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
Fully Compatible With TTL Input and  
Output Logic Levels  
64-mA Output Sink Current  
32-mA Output Source Current  
description  
The CY74FCT399T is a high-speed quad 2-input register that selects four bits of data from either of two sources  
(ports) under control of a common select (S) input. Selected data are transferred to a 4-bit output register  
synchronous with the low-to-high transition of the clock (CP) input. The 4-bit D-type output register is fully edge  
triggered. The data inputs (I , I ) and S input must be stable only one setup time prior to, and hold time after,  
0X 1X  
the low-to-high transition of CP for predictable operation. The CY74FCT399T has noninverted outputs.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
PIN DESCRIPTION  
NAME  
S
DESCRIPTION  
Common select input  
CP  
Clock-pulse input (active rising edge)  
Data inputs from source 0  
I
I
0
Data inputs from source 1  
1
Q
Register noninverted outputs  
ORDERING INFORMATION  
SPEED  
(ns)  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
Tube  
6.1  
6.1  
7
CY74FCT399CTSOC  
CY74FCT399CTSOCT  
CY74FCT399ATSOC  
CY74FCT399ATSOCT  
SOIC – SO  
SOIC – SO  
FCT399C  
FCT399A  
Tape and reel  
Tube  
–40°C to 85°C  
Tape and reel  
7
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

与CY74FCT399CTSOCE4相关器件

型号 品牌 获取价格 描述 数据表
CY74FCT399CTSOCG4 TI

获取价格

FCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, SOIC
CY74FCT399CTSOCT TI

获取价格

Quad 2-Input Register
CY74FCT399CTSOCTE4 TI

获取价格

Quad 2-Input Register
CY74FCT399T TI

获取价格

Quad 2-Input Register
CY74FCT399TPC CYPRESS

获取价格

D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 4-Bit, True Output, CMOS, PDIP16
CY74FCT399TQC CYPRESS

获取价格

D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 4-Bit, True Output, CMOS, PDSO16
CY74FCT399TSOIC TI

获取价格

Quad 2-Input Register
CY74FCT480ATPC TI

获取价格

Dual 8-Bit Parity Generator/Checker
CY74FCT480ATQC CYPRESS

获取价格

Parity Generator/Checker, FCT Series, 8-Bit, True Output, CMOS, PDSO24, 0.150 INCH, QSOP-2
CY74FCT480ATQCT TI

获取价格

Dual 8-Bit Parity Generator/Checker