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CY74FCT377TSOIC

更新时间： 2024-11-25 05:18:59

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
7页	74K
描述
8-Bit Register

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数据手册

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CY74FCT377TSOIC 数据手册

1CY54/74FCT377T

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY54/74FCT377T

8-Bit Register

SCCS023 - May1994 - Revised March 2000

• Clock Enable for address and data synchronization

Features

application

• Function, pinout and drive compatible with FCT and

• Eight edge-triggered D ﬂip-ﬂops

• Extended commercial range of −40˚C to +85˚C

F logic

• FCT-C speed at 5.2 ns max. (Com’l)

FCT-A speed at 7.2 ns max. (Com’l)

• Reduced V_OH(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

• Power-off disable feature

• Matched rise and fall times

• ESD > 2000V

Functional Description

The FCT377T has eight triggered D-type ﬂip-ﬂops with

individual D inputs. The common buffered clock inputs (CP)

loads all ﬂip-ﬂops simultaneously when the Clock Enable (CE)

is LOW. The register is fully edge-triggered. The state of each

D input, one set-up time before the LOW-to-HIGH clock

transition, is transferred to the corresponding ﬂip-ﬂop’s O out-

put. The CE input must be stable only one set-up time prior to

the LOW-to-HIGH clock transition for predictable operation.

• Fully compatible with TTL input and output logic levels

• Sink Current

64 mA (Com’l),

32 mA (Mil)

32 mA (Com’l),

12 mA (Mil)

The outputs are designed with a power-off disable feature to

allow for live insertion of boards.

Source Current

Logic Block Diagram

Pin Configurations

Logic Symbol

SOIC/QSOP

Top View

LCC

Top View

6 5 4

GND

1516 17 18

GND

12 3 4 5 6 7

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