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CY74FCT2543TSOIC PDF预览

CY74FCT2543TSOIC

更新时间： 2024-01-08 18:19:10
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
6页 58K
描述
8-Bit Latched Transceiver

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中文翻译

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CY74FCT2543TSOIC 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SSOP, SSOP24,.24
针数：24Reach Compliance Code：unknown
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.23Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：FCTJESD-30 代码：R-PDSO-G24
长度：8.65 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.012 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP24,.24
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 VProp。Delay @ Nom-Sup：8.5 ns
传播延迟（tpd）：12.5 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：3.9 mm
Base Number Matches：1

CY74FCT2543TSOIC 数据手册

 浏览型号CY74FCT2543TSOIC的Datasheet PDF文件第2页浏览型号CY74FCT2543TSOIC的Datasheet PDF文件第3页浏览型号CY74FCT2543TSOIC的Datasheet PDF文件第4页浏览型号CY74FCT2543TSOIC的Datasheet PDF文件第5页浏览型号CY74FCT2543TSOIC的Datasheet PDF文件第6页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT2543T  
SCCS042 - September 1994 - Revised March 2000  
8-Bit Latched Transceiver  
Features  
Functional Description  
• Function and pinout compatible with FCT and F logic  
• FCT-C speed at 5.3 ns max.  
FCT-A speed at 6.5 ns max.  
• 25Ω output series resistors to reduce transmission line  
reflection noise  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature  
• Matched rise and fall times  
The FCT2543T Octal Latched Tranceiver contains two sets of  
eight D-type latches. Separate Latch Enable (LEAB, LEBA)  
and Output Enable (OEAB, OEBA) permits each latch set to  
have independent control of inputting and outputting in either  
direction of data flow. For data flow from A to B, for example,  
the A-to-B Enable (CEAB) input must be LOW to enter data  
from A or to take data from B, as indicated in the truth table.  
With CEAB LOW, a LOW signal on the A-to-B Latch Enable  
(LEAB) input makes the A-to-B latches transparent; a subse-  
quent LOW-to-HIGH transition of the LEAB signal puts the A  
latches in the storage mode and their output no longer change  
with the A inputs. With CEAB and OEAB both LOW, the  
three-state B output buffers are active and reflect data present  
at the output of the A latches. Control of data from B to A is  
similar, but uses CEAB, LEAB, and OEAB inputs. On-chip ter-  
mination resistors have been added to the outputs to reduce  
system noise caused by reflections. The FCT2543T can be  
used to replace the FCT543T to reduce noise in an existing  
design.  
• Fully compatible with TTL input and output logic levels  
• Sink current  
Source current  
12 mA  
15 mA  
• Separation controls for data flow in each direction  
• Back to back latches for storage  
• ESD > 2000V  
• Extended commercial temp. range of –40˚C to +85˚C  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
Functional Block Diagram  
Pin Configurations  
Detail A  
SOIC/QSOP  
Top View  
B
D Q  
LE  
0
LEBA  
OEBA  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
A
0
Q D  
LE  
CEBA  
A
0
B
0
A
1
B
1
B
B
B
B
B
B
B
A
A
2
B
2
1
2
3
4
5
6
7
1
A
2
A
3
B
3
A
4
B
4
A
3
A
5
B
5
A
4
Detail A x 7  
A
6
B
6
A
5
A
7
B
7
10  
11  
12  
15  
14  
13  
A
6
CEAB  
GND  
LEAB  
OEAB  
A
7
OEBA  
FCT2543T–3  
OEAB  
CEBA  
LEBA  
CEAB  
LEAB  
FCT2543T–1  
Copyright © 2000, Texas Instruments Incorporated  
123456

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