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CY74FCT16823TSSOP

更新时间： 2024-11-14 09:42:59
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德州仪器 - TI /
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8页 72K
描述
18-Bit Registers

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CY74FCT16823TSSOP 数据手册

 浏览型号CY74FCT16823TSSOP的Datasheet PDF文件第2页浏览型号CY74FCT16823TSSOP的Datasheet PDF文件第3页浏览型号CY74FCT16823TSSOP的Datasheet PDF文件第4页浏览型号CY74FCT16823TSSOP的Datasheet PDF文件第5页浏览型号CY74FCT16823TSSOP的Datasheet PDF文件第6页浏览型号CY74FCT16823TSSOP的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT16823T  
CY74FCT162823T  
SCCS062 - August 1994 - Revised March 2000  
18-Bit Registers  
CY74FCT162823T Features:  
Features  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,  
TA= 25˚C  
• FCT-E speed at 4.4 ns  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
Functional Description  
• Typical output skew < 250 ps  
• ESD > 2000V  
The CY74FCT16823T and the CY74FCT162823T 18-bit bus  
interface registers are designed for use in high-speed,  
low-power systems needing wide registers and parity. 18-bit  
operation is achieved by connecting the control lines of the two  
9-bit registers. Flow-through pinout and small shrink  
packaging aids in simplifying board layout. The outputs are  
designed with a power-off disable feature to allow live insertion  
of boards.  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
• Industrial temperature range of −40˚C to +85˚C  
• VCC = 5V ± 10%  
CY74FCT16823T Features:  
• 64 mA sink current, 32 mA source current  
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,  
TA = 25˚C  
The CY74FCT16823T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
The CY74FCT162823T has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162823T is ideal for driving transmission lines.  
Logic Block Diagrams  
Pin Configuration  
SSOP/TSSOP  
OE  
1
Top View  
CLR  
1
CLK  
56  
55  
54  
53  
52  
51  
50  
1
1
CLR  
1
2
3
4
5
6
1
CLKEN  
D
OE  
1
CLK  
1
Q
1
1
1
1
GND  
Q
GND  
D
CLKEN  
1
1
1
2
3
1
1
2
3
Q
D
V
CC  
V
CC  
7
R
C
D
Q
D
1
1
1
4
5
1
1
4
49  
48  
47  
46  
8
Q
1
1
D
5
Q
9
D
Q
1
6
6
D
10  
11  
12  
1
1
GND  
GND  
Q
D
D
1
7
1
1
1
7
8
45  
44  
43  
42  
41  
Q
Q
1
1
8
9
13  
14  
FCT16823-1  
D
9
TO 8 OTHER CHANNELS  
D
D
Q
Q
Q
2
2
1
2
2
2
1
15  
16  
17  
OE  
2
2
2
3
D
2
3
40  
39  
38  
CLR  
2
GND  
Q
GND  
D
18  
19  
20  
21  
22  
23  
2
2
2
4
5
6
2
2
4
5
6
CLK  
2
D
D
Q
Q
37  
36  
35  
34  
2
CLKEN  
2
V
CC  
V
CC  
7
Q
Q
D
2
2
7
2
2
33  
32  
31  
30  
29  
D
8
8
24  
25  
R
C
D
GND  
Q
GND  
D
Q
1
2
9
26  
27  
28  
2
2
9
OE  
CLKEN  
CLK  
2
2
2
D
2
2
CLR  
2
FCT16823-3  
FCT16823-2  
TO 8 OTHER CHANNELS  
Copyright © 2000, Texas Instruments Incorporated  
12345678

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