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CY74FCT16652

更新时间： 2024-01-15 13:53:01
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
16页 315K
描述
16-Bit Registered Transceivers

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中文翻译

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CY74FCT16652 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknown风险等级：5.13
其他特性：SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA系列：FCT
JESD-30 代码：R-PDSO-G56长度：18.415 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：9 ns认证状态：Not Qualified
座面最大高度：2.794 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

CY74FCT16652 数据手册

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1CY74FCT162652T  
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT16652T  
CY74FCT162652T  
SCCS061B - July 1994 - Revised September 2001  
16-Bit Registered Transceivers  
Features  
Functional Description  
• Ioff supports partial-power-down mode operation  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Typical output skew < 250 ps  
• ESD > 2000V  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
These 16-bit, high-speed, low-power, registered transceivers  
that are organized as two independent 8-bit bus transceivers  
with three-state D-type registers and control circuitry arranged  
for multiplexed transmission of data directly from the input bus  
or from the internal storage registers. OEAB and OEBA control  
pins are provided to control the transceiver functions. SAB and  
SBA control pins are provided to select either real-time or  
stored data transfer.  
• Industrial temperature range of −40˚C to +85˚C  
• VCC = 5V ± 10%  
Data on the A or B data bus, or both, can be stored in the  
internal D flip-flops by LOW-to-HIGH transitions at the  
appropriate clock pins (CLKAB or CLKBA), regardless of the  
select or enable control pins. When SAB and SBA are in the  
real-time transfer mode, it is also possible to store data without  
using the internal D-type flip-flops by simultaneously enabling  
OEAB and OEBA. In this configuration, each output reinforces  
its input. Thus, when all other data sources to the two sets of  
bus lines are at high impedance, each set of bus lines will  
remain at its last state.  
CY74FCT16652T Features:  
• 64 mA sink current, 32 mA source current  
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,  
TA = 25˚C  
CY74FCT162652T Features:  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,  
TA= 25˚C  
This device is fully specified for partial-power-down  
applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device  
when it is powered down.  
The CY74FCT16652T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
The CY74FCT162652T has 24-mA balanced output drivers  
with current-limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162652T is ideal for driving transmission lines.  
Logic Block Diagrams  
OEAB  
1
OEAB  
2
OEBA  
1
OEBA  
2
CLKBA  
1
1
CLKBA  
2
SBA  
2
SBA  
1
CLKAB  
CLKAB  
2
SAB  
2
SAB  
1
B REG  
D
B REG  
D
C
C
A
1
2
A
1
1
A REG  
A REG  
D
C
D
C
B
B
1
1
1
2
TO 7 OTHER CHANNELS  
FCT16652-1  
FCT16652-2  
TO 7 OTHER CHANNELS  
Copyright © 2001, Texas Instruments Incorporated  
1234567...16

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