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CY74FCT16646TPVCR PDF预览

CY74FCT16646TPVCR

更新时间： 2024-09-25 13:07:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 77K
描述
IC FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-56, Bus Driver/Transceiver

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CY74FCT16646TPVCR 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：0.300 INCH, GREEN, PLASTIC, SSOP-56针数：56
Reach Compliance Code：unknown风险等级：5.08
Is Samacsys：N系列：FCT
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.415 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：9 ns认证状态：Not Qualified
座面最大高度：2.79 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.49 mm
Base Number Matches：1

CY74FCT16646TPVCR 数据手册

 浏览型号CY74FCT16646TPVCR的Datasheet PDF文件第2页浏览型号CY74FCT16646TPVCR的Datasheet PDF文件第3页浏览型号CY74FCT16646TPVCR的Datasheet PDF文件第4页浏览型号CY74FCT16646TPVCR的Datasheet PDF文件第5页浏览型号CY74FCT16646TPVCR的Datasheet PDF文件第6页浏览型号CY74FCT16646TPVCR的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT16646T  
CY74FCT162646T  
SCCS060 - August 1994 - Revised March 2000  
16-Bit Registered Transceivers  
Features  
Functional Description  
• FCT-E speed at 3.8 ns  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Typical output skew < 250 ps  
• ESD > 2000V  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
• Industrial temperature range of −40˚C to +85˚C  
• VCC = 5V ± 10%  
The CY74FCT16646T and CY74FCT162646T 16-bit  
transceivers are three-state, D-type registers, and control  
circuitry arranged for multiplexed transmission of data directly  
from the input bus or from the internal registers. Data on the A  
or B bus will be clocked into the registers as the appropriate  
clock pin goes to a HIGH logic level. Output Enable (OE) and  
direction pins (DIR) are provided to control the transceiver  
function. In the transceiver mode, data present at the high  
impedance port may be stored in either the A or B register, or  
in both. The select controls can multiplex stored and real-time  
(transparent mode) data. The direction control determines  
which bus will receive data when the Output Enable (OE) is  
Active LOW. In the isolation mode (Output Enable (OE) HIGH),  
A data may be stored in the B register and/or B data may be  
stored in the A register. The output buffers are designed with  
a power-off disable feature that allows live insertion of boards.  
CY74FCT16646T Features:  
• 64 mA sink current, 32 mA source current  
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,  
TA = 25˚C  
The CY74FCT16646T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
CY74FCT162646T Features:  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,  
TA= 25˚C  
The CY74FCT162646T has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162646T is ideal for driving transmission lines.  
Logic Block Diagrams  
OE  
2
OE  
1
DIR  
2
DIR  
CLKBA  
SBA  
CLKAB  
1
CLKBA  
2
1
SBA  
CLKAB  
2
1
2
1
SAB  
2
SAB  
1
B REG  
D
B REG  
D
C
C
A
2 1  
A REG  
D
B
2
1
A REG  
D
B
1
1
A
1 1  
C
C
FCT16646-2  
TO 7 OTHER CHANNELS  
FCT16646-1  
TO 7 OTHER CHANNELS  
Copyright © 2000, Texas Instruments Incorporated  
1234567...9

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