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CY74FCT16543TPVCR

更新时间： 2024-11-14 13:07:11
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德州仪器 - TI /
页数 文件大小 规格书
8页 72K
描述
FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, 0.635 MM PITCH, GREEN, PLASTIC, SSOP-56

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CY74FCT16543TPVCR 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.06系列：FCT
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.415 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：12.5 ns认证状态：Not Qualified
座面最大高度：2.79 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.49 mm
Base Number Matches：1

CY74FCT16543TPVCR 数据手册

 浏览型号CY74FCT16543TPVCR的Datasheet PDF文件第2页浏览型号CY74FCT16543TPVCR的Datasheet PDF文件第3页浏览型号CY74FCT16543TPVCR的Datasheet PDF文件第4页浏览型号CY74FCT16543TPVCR的Datasheet PDF文件第5页浏览型号CY74FCT16543TPVCR的Datasheet PDF文件第6页浏览型号CY74FCT16543TPVCR的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT16543T  
CY74FCT162543T  
CY74FCT162H543T  
SCCS059 - August 1994 - Revised March 2000  
16-Bit Latched Transceivers  
Features  
Functional Description  
• FCT-E speed at 3.4 ns  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Typical output skew < 250 ps  
• ESD > 2000V  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
• Industrial temperature range of −40˚C to +85˚C  
• VCC = 5V ± 10%  
The CY74FCT16543T and CY74FCT162543T are 16-bit,  
high-speed, low power latched transceivers that are organized as two  
independent 8-bit D-type latched transceivers containing two sets of  
eight D-type latches with separate Latch Enable (LEAB, LEAB) and  
Output Enable (OEAB, OEAB) controls for each set to permit  
independent control of inputting and outputting in either direction of  
data flow. For data flow from A to B, for example, the A-to-B input  
Enable (CEAB) must be LOW in order to enter data from A or to take  
data from B as indicated in the truth table. With CAEB LOW, a LOW  
signal on the A-to-B Latch Enable (LEAB) makes the A-to-B latches  
transparent; a subsequent LOW-to-HIGH transition of the LEAB  
signal puts the A latches in the storage mode and their outputs no  
longer change with the A inputs. With CEAB and OEAB both LOW,  
the three-state B output buffers are active and reflect the data present  
at the output of the A latches. Control of data from B to A is similar,  
but uses CEAB, LEAB, and OEAB inputs flow-through pinout and  
small shrink packaging and in simplifying board design. The output  
buffers are designed with a power-off disable feature to allow live  
insertion of boards.  
CY74FCT16543T Features:  
• 64 mA sink current, 32 mA source current  
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,  
TA = 25˚C  
CY74FCT162543T Features:  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,  
TA= 25˚C  
The CY74FCT16543T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
The CY74FCT162543T has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162543T is ideal for driving transmission lines.  
CY74FCT162H543T Features:  
• Bus hold retains last active state  
• Eliminates the need for external pull-up or pull-down  
resistors  
The CY74FCT162H543T is a 24-mA balanced output part that  
has “bus hold” on the data inputs. The device retains the  
input’s last state whenever the input goes to high impedance.  
This eliminates the need for pull-up/down resistors and  
prevents floating inputs.  
Copyright © 2000, Texas Instruments Incorporated  
12345678

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