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CY74FCT163H952CPVCT

更新时间： 2024-01-13 19:10:54
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
6页 68K
描述
FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56

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CY74FCT163H952CPVCT 技术参数

生命周期：Obsolete包装说明：SSOP,
Reach Compliance Code：unknown风险等级：5.5
其他特性：BUS HOLD I/P'S系列：FCT
JESD-30 代码：R-PDSO-G56长度：18.415 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：6.3 ns
认证状态：Not Qualified座面最大高度：2.79 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

CY74FCT163H952CPVCT 数据手册

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1CY74FCT163952  
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT163952  
CY74FCT163H952  
SCCS048 - March 1997 - Revised March 2000  
16-Bit Registered Transceivers  
Features  
Functional Description  
• Low power, pin-compatible replacement for LCX and  
LPT families  
• 5V tolerant inputs and outputs  
These 16-bit registered transceivers are high-speed,  
low-power devices. 16-bit operation is achieved by connecting  
the control lines of the two 8-bit registered transceivers  
together. For data flow from bus A-to-B, CEAB must be LOW  
to allow data to be stored when CLKAB transitions from  
LOW-to-HIGH. The stored data will be present on the output  
when OEAB is LOW. Control of data from B-to-A is similar and  
is controlled by using the CEBA, CLKBA, and OEBA inputs.  
The outputs are 24-mA balanced output drivers with current  
limiting resistors to reduce the need for external terminating  
resistors and provide for minimal undershoot and reduced  
ground bounce.  
• 24 mA balanced drive outputs  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for reduced noise  
• FCT-C speed at 4.4 ns  
• Latch-up performance exceeds JEDEC standard no. 17  
• Typical output skew < 250 ps  
• Industrial temperature range of –40˚C to +85˚C  
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)  
The CY74FCT163H952 has “bus hold” on the data inputs,  
which retains the input’s last state whenever the source driving  
the input goes to high impedance. This eliminates the need for  
pull-up/down resistors and prevents floating inputs.  
• TypicalV  
olp  
(groundbounce)performanceexceedsMil  
Std 883D  
• VCC = 2.7V to 3.6V  
• ESD (HBM) > 2000V  
CY74FCT163H952  
The CY74FCT163952 is designed with inputs and outputs  
capable of being driven by 5.0V buses, allowing its use in  
mixed voltage systems as a translator. The outputs are also  
designed with a power off disable feature enabling its use in  
applications requiring live insertion.  
• Bus hold on data inputs  
• Eliminates the need for external pull-up or pull-down  
resistors  
• Devices with bus hold are not recommended for trans-  
lating rail-to-rail CMOS signals to 3.3V logic levels  
Pin Configuration  
Logic Block Diagrams; CY74FCT163952, CY74FCT163H952  
SSOP/TSSOP  
Top View  
OEAB  
1
2
56  
55  
OEBA  
CLKBA  
1
1
1
CEBA  
CEBA  
2
2
1
CLKAB  
1
CEAB  
1
CEBA  
3
4
54  
53  
1
CLKBA  
OEAB  
CLKBA  
OEAB  
1
GND  
A
GND  
B
1
2
5
6
7
52  
51  
50  
1
1
1
1
CEAB  
CEAB  
1
2
B
2
A
1
1
2
V
V
CC  
CC  
A
CLKAB  
OEBA  
CLKAB  
OEBA  
2
1
2
B
3
8
9
49  
48  
1
3
1
A
B
4
1
1
4
1
B
5
A
5
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
1
C
C
1
A
A
2 1  
CE  
D
CE  
D
GND  
B
1
1
GND  
A
B
B
2
1
1
1
1
1
6
1
1
6
C
CE  
D
C
CE  
D
A
7
B
7
A
B
1 8  
1
8
A
B
2 1  
2
1
B
A
2
2
2
2
2
B
3
A
2
3
GND  
A
GND  
B
TO7 OTHERCHANNELS  
TO7 OTHERCHANNELS  
2
4
2
4
A
5
B
2 5  
2
B
A
2
6
2
6
V
CC  
V
CC  
B
7
A
2
2
2
7
B
8
A
24  
25  
26  
27  
28  
33  
32  
31  
30  
29  
2
8
GND  
GND  
CEBA  
2
CEAB  
2
CLKAB  
CLKBA  
OEBA  
2
2
2
OEAB  
2
Copyright © 2000, Texas Instruments Incorporated  
123456

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