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CY74FCT163652CPAC

更新时间： 2024-02-24 12:22:55
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
12页 142K
描述
16-Bit Registered Transceiver

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中文翻译

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CY74FCT163652CPAC 技术参数

生命周期：Transferred零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknown风险等级：5.49
Is Samacsys：N其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列：FCTJESD-30 代码：R-PDSO-G56
长度：18.415 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：5.7 ns
认证状态：Not Qualified座面最大高度：2.794 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

CY74FCT163652CPAC 数据手册

 浏览型号CY74FCT163652CPAC的Datasheet PDF文件第2页浏览型号CY74FCT163652CPAC的Datasheet PDF文件第3页浏览型号CY74FCT163652CPAC的Datasheet PDF文件第4页浏览型号CY74FCT163652CPAC的Datasheet PDF文件第5页浏览型号CY74FCT163652CPAC的Datasheet PDF文件第6页浏览型号CY74FCT163652CPAC的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT163652  
SCCS052 - March 1997 - Revised March 2000  
16-Bit Registered Transceiver  
Features  
Functional Description  
• Low power, pin-compatible replacement for LCX and  
LPT families  
• 5V tolerant inputs and outputs  
The CY74FCT163652 is a 16-bit, high-speed, low-power,  
registered transceiver that is organized as two independent  
8-bit bus transceivers with three-state D-type registers and  
control circuitry arranged for multiplexed transmission of data  
directly from the input bus or from the internal storage  
registers. OEAB and OEBA control pins are provided to control  
the transceiver functions. SAB and SBA control pins are  
provided to select either real-time or stored data transfer.  
• 24 mA balanced drive outputs  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for reduced noise  
• FCT-C speed at 4.6 ns  
• Latch-up performance exceeds JEDEC standard no. 17  
• ESD > 2000V per MIL-STD-883D, Method 3015  
• Typical output skew < 250 ps  
• Industrial temperature range of –40˚C to +85˚C  
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)  
• Typical Volp (ground bounce) performance exceeds Mil  
Std 883D  
• VCC = 2.7V to 3.6V  
Data on the A or B data bus, or both, can be stored in the  
internal D flip-flops by LOW-to-HIGH transitions at the  
appropriate clock pins (CLKAB or CLKBA), regardless of the  
select or enable control pins. When SAB and SBA are in the  
real-time transfer mode, it is also possible to store data without  
using the internal D-type flip-flops by simultaneously enabling  
OEAB and OEBA. In this configuration, each output reinforces  
its input. Thus, when all other data sources to the two sets of  
bus lines are at high impedance, each set of bus lines will  
remain at its last state.  
The CY74FCT163652 has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The inputs  
and outputs were designed to be capable of being driven by  
5.0V buses, allowing them to be used in mixed voltage  
systems as translators. The outputs are also designed with a  
power-off disable feature enabling them to be used in  
applications requiring live insertion.  
Logic Block Diagrams  
OEAB  
1
OEAB  
2
OEBA  
1
OEBA  
2
CLKBA  
1
1
CLKBA  
2
SBA  
2
SBA  
1
CLKAB  
CLKAB  
2
SAB  
2
SAB  
1
B REG  
D
B REG  
D
C
C
A
1
2
A
1
1
A REG  
A REG  
D
C
D
C
B
B
1
1
1
2
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
Copyright © 2000, Texas Instruments Incorporated  
1234567...12

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