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CY74FCT163646SSOP PDF预览

CY74FCT163646SSOP

更新时间： 2024-02-18 19:37:46
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
8页 73K
描述
16-Bit Registered Transceiver

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CY74FCT163646SSOP 技术参数

生命周期：Transferred零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknown风险等级：5.47
Is Samacsys：N其他特性：WITH DIRECTION CONTROL
系列：FCTJESD-30 代码：R-PDSO-G56
长度：18.415 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：5.7 ns
认证状态：Not Qualified座面最大高度：2.794 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

CY74FCT163646SSOP 数据手册

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1CY74FCT163646  
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT163646  
SCCS058 - March 1997 - Revised March 2000  
16-Bit Registered Transceiver  
Features  
Functional Description  
• Low power, pin-compatible replacement for LCX and  
LPT families  
• 5V tolerant inputs and outputs  
The CY74FCT163646 16-bit transceiver is a three-state,  
D-type register, and control circuitry arranged for multiplexed  
transmission of data directly from the input bus or from the  
internal registers. Data on the A or B bus will be clocked into  
the registers as the appropriate clock pin goes to a HIGH logic  
level. Output Enable (OE) and direction pins (DIR) are  
provided to control the transceiver function. In the transceiver  
mode, data present at the high impedance port may be stored  
in either the A or B register, or in both. The select controls can  
multiplex stored and real-time (transparent mode) data. The  
direction control determines which bus will receive data when  
the Output Enable (OE) is Active LOW. In the isolation mode  
(Output Enable (OE) HIGH), A data may be stored in the B  
register and/or B data may be stored in the A register.  
• 24 mA balanced drive outputs  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for reduced noise  
• FCT-C speed at 5.4 ns  
• Latch-up performance exceeds JEDEC standard no. 17  
• ESD > 2000V per MIL-STD-883D, Method 3015  
• Typical output skew < 250 ps  
• Industrial temperature range of –40˚C to +85˚C  
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)  
• Typical Volp (ground bounce) performance exceeds Mil  
Std 883D  
• VCC = 2.7V to 3.6V  
The CY74FCT163646 has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The inputs  
and outputs were designed to be capable of being driven by  
5.0V buses, allowing them to be used in mixed voltage  
systems as translators. The outputs are also designed with a  
power-off disable feature enabling them to be used in  
applications requiring live insertion.  
Logic Block Diagrams  
OE  
2
OE  
1
DIR  
2
DIR  
CLKBA  
SBA  
CLKAB  
1
CLKBA  
2
1
SBA  
CLKAB  
2
1
2
1
SAB  
2
SAB  
1
B REG  
D
B REG  
D
C
C
A REG  
D
B
2
1
A REG  
D
B
1
1
A
2 1  
A
1 1  
C
C
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
Copyright © 2000, Texas Instruments Incorporated  
12345678

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