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CY74FCT163543

更新时间： 2024-11-07 05:31:03
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德州仪器 - TI /
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16-Bit Latched Transceiver

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CY74FCT163543 数据手册

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1CY74FCT163543  
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT163543  
SCCS063A - June 1997 - Revised April 2000  
16-Bit Latched Transceiver  
Features  
Functional Description  
• Low power, pin-compatible replacement for LCX and  
LPT families  
• 5V tolerant inputs and outputs  
The CY74FCT163543 is a 16-bit, high-speed, low power latched  
transceiver that is organized as two independent 8-bit D-type latched  
transceivers, containing twosetsofeightD-typelatcheswithseparate  
Latch Enable (LEAB, LEAB) and Output Enable (OEAB, OEAB) con-  
trols for each set to permit independent control of inputting and out-  
putting in either direction of data flow. For data flow from A to B, for  
example, the A-to-B input Enable (CEAB) must be LOW in order to  
enter data from A or to take data from B, as indicated in the truth table.  
With CAEB LOW, a LOW signal on the A-to-B Latch Enable (LEAB)  
makes the A-to-B latches transparent; a subsequent LOW-to-HIGH  
transition of the LEAB signal puts the A latches in the storage mode  
and their outputs no longer follow the A inputs. With CEAB and OEAB  
both LOW, the three-state B output buffers are active and reflect the  
data present at the output of the A latches. Control of data from B to  
A is similar, but uses CEAB, LEAB, and OEAB inputs.  
• 24 mA balanced drive outputs  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for reduced noise  
• FCT-C speed at 5.1 ns  
• Latch-up performance exceeds JEDEC standard no. 17  
• ESD > 2000V per MIL-STD-883D, Method 3015  
• Typical output skew < 250 ps  
• Industrial temperature range of –40˚C to +85˚C  
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)  
• Typical Volp (ground bounce) performance exceeds Mil  
Std 883D  
The CY74FCT163543 has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The inputs  
and outputs are capable of being driven by 5.0V buses, allow-  
ing them to be used in mixed voltage systems as translators.  
The outputs are also designed with a power off disable feature  
enabling them to be used in applications requiring live inser-  
tion. Flow-through pinout and small shrink packaging simplify board  
design.  
• VCC = 2.7V to 3.6V  
Logic Block Diagrams  
PinConfiguration  
OEBA  
1
Top View  
SSOP/TSSOP  
CEBA  
1
LEBA  
1
OEAB  
OEBA  
1
2
56  
55  
1
1
OEAB  
1
LEAB  
LEBA  
1
1
CEAB  
1
CEAB  
1
3
4
54  
53  
CEBA  
1
LEAB  
1
GND  
A
GND  
B
C
D
5
6
7
52  
51  
50  
1
1
1
1
2
A
1
1
B
1
1
A
1
B
1
2
V
V
CC  
CC  
C
D
A
B
1
3
4
5
8
9
49  
48  
1
3
4
5
A
1
B
1
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
B
1
1
GND  
A
GND  
B
1
6
1
6
TO 7 OTHER CHANNELS  
A
1
B
1
7
8
7
8
A
1
B
1
OEBA  
2
A
2
B
2
1
1
CEBA  
2
A
B
2
B
2
2
2
3
2
3
A
2
LEBA  
2
GND  
A
GND  
B
OEAB  
2
2
4
5
2
4
5
A
2
B
2
CEAB  
2
A
B
2
6
2
6
LEAB  
2
V
V
CC  
CC  
C
D
A
2
1
A
2
B
2
7
8
7
8
B
2
1
A
2
B
2
24  
25  
26  
27  
28  
33  
32  
31  
30  
29  
GND  
GND  
C
D
CEAB  
LEAB  
OEAB  
CEBA  
2
LEBA  
2
OEBA  
2
2
2
2
TO 7 OTHER CHANNELS  
Copyright © 2000, Texas Instruments Incorporated  
1234567

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