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CY74FCT163500APVCT PDF预览

CY74FCT163500APVCT

更新时间: 2024-01-29 00:51:07
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
7页 66K
描述
18-Bit Registered Transceiver

CY74FCT163500APVCT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP56,.4针数:56
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.31
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:FCTJESD-30 代码:R-PDSO-G56
长度:18.415 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A位数:18
功能数量:1端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP56,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/3.3 VProp。Delay @ Nom-Sup:4.6 ns
传播延迟(tpd):5.3 ns认证状态:Not Qualified
座面最大高度:2.79 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:NEGATIVE EDGE
宽度:7.5 mmBase Number Matches:1

CY74FCT163500APVCT 数据手册

 浏览型号CY74FCT163500APVCT的Datasheet PDF文件第2页浏览型号CY74FCT163500APVCT的Datasheet PDF文件第3页浏览型号CY74FCT163500APVCT的Datasheet PDF文件第4页浏览型号CY74FCT163500APVCT的Datasheet PDF文件第5页浏览型号CY74FCT163500APVCT的Datasheet PDF文件第6页浏览型号CY74FCT163500APVCT的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT163500  
SCCS066 - June 1997 - Revised March 2000  
18-Bit Registered Transceiver  
Features  
Functional Description  
• Low power, pin-compatible replacement for LCX and  
LPT families  
• 5V tolerant inputs and outputs  
The CY74FCT163500 is an 18-bit universal bus transceiver  
that can be operated in transparent, latched, or clock modes  
by combining D-type latches and D-type flip-flops. Data flow in  
each direction is controlled by output-enable (OEAB and  
OEBA), latch enable (LEAB and LEBA), and clock inputs  
(CLKAB and CLKBA) inputs. For A-to-B data flow, the device  
operates in transparent mode when LEAB is HIGH. When  
LEAB is LOW, the A data is latched if CLKAB is held at a HIGH  
or LOW logic level. If LEAB is LOW, the A bus data is stored in  
the latch/flip-flop on the HIGH-to-LOW transition of CLKAB.  
OEAB performs the output enable function on the B port. Data  
flow from B-to-A is similar to that of A-to-B and is controlled by  
OEBA, LEBA, and CLKBA.  
• 24 mA balanced drive outputs  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for reduced noise  
• FCT-C speed at 4.6 ns  
• Latch-up performance exceeds JEDEC standard no. 17  
• ESD > 2000V per MIL-STD-883D, Method 3015  
• Typical output skew < 250ps  
• Industrial temperature range of –40˚C to +85˚C  
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)  
• Typical Volp (ground bounce) performance exceeds Mil  
Std 883D  
The CY74FCT163500 has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce.The inputs  
and outputs are capable of being driven by 5.0V busses,  
allowing them to be used in mixed voltage systems as  
translators. The outputs are also designed with a power off  
disable feature enabling them to be used in applications  
requiring live insertion.  
• VCC = 2.7V to 3.6V  
Logic Block Diagram  
Pin Configuration  
SSOP/TSSOP  
Top View  
GND  
1
2
3
4
56  
55  
54  
OEAB  
LEAB  
CLKAB  
B
1
A
1
OEAB  
GND  
GND  
53  
52  
51  
50  
B
2
A
2
5
6
CLKBA  
B
V
A
3
3
V
CC  
CC  
LEBA  
OEBA  
7
B
A
4
4
5
6
49  
48  
47  
46  
8
A
A
B
B
5
6
9
CLKAB  
LEAB  
10  
11  
GND  
GND  
A
7
B
7
45  
44  
43  
12  
13  
A
A
B
B
B
8
9
8
C
D
C
D
14  
15  
16  
17  
18  
9
B
1
A
10  
42  
41  
A
1
10  
A
A
B
11  
B
12  
11  
12  
40  
39  
38  
GND  
GND  
C
D
C
D
A
A
A
B
13  
14  
15  
19  
20  
21  
22  
23  
13  
14  
15  
B
37  
36  
35  
34  
B
V
V
CC  
CC  
B
16  
A
16  
17  
A
33  
32  
31  
30  
29  
B
17  
24  
25  
TO 17 OTHER CHANNELS  
GND  
GND  
A
B
18  
26  
27  
28  
18  
OEBA  
LEBA  
CLKBA  
GND  
Copyright © 2000, Texas Instruments Incorporated  

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