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CY74FCT162841TTSSOP

更新时间： 2024-09-25 04:02:03
品牌 Logo 应用领域
德州仪器 - TI 锁存器
页数 文件大小 规格书
6页 62K
描述
20-Bit Latches

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中文翻译

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CY74FCT162841TTSSOP 数据手册

 浏览型号CY74FCT162841TTSSOP的Datasheet PDF文件第2页浏览型号CY74FCT162841TTSSOP的Datasheet PDF文件第3页浏览型号CY74FCT162841TTSSOP的Datasheet PDF文件第4页浏览型号CY74FCT162841TTSSOP的Datasheet PDF文件第5页浏览型号CY74FCT162841TTSSOP的Datasheet PDF文件第6页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT16841T  
CY74FCT162841T  
SCCS067 - July 1994 - Revised March 2000  
20-Bit Latches  
Features  
Functional Description  
• FCT-C speed at 5.5 ns (FCT16841T Com’l)  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Typical output skew < 250 ps  
• ESD > 2000V  
The CY74FCT16841T and CY74FCT162841T are 20-bit  
D-type latches designed for use in bus applications requiring  
high speed and low power. These devices can be used as two  
independent 10-bit latches, or as a single 10-bit latch, or as a  
single 20-bit latch by connecting the Output Enable (OE) and  
Latch (LE) inputs. Flow-through pinout and small shrink  
packaging aid in simplifying board layout. The output buffers  
are designed with a power-off disable feature to allow live  
insertion of boards.  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
• Industrial temperature range of −40˚C to +85˚C  
• VCC = 5V ± 10%  
The CY74FCT16841T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
The CY74FCT162841T has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162841T is ideal for driving transmission lines.  
CY74FCT16841T Features:  
• 64 mA sink current, 32 mA source current  
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,  
TA = 25˚C  
CY74FCT162841T Features:  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,  
TA= 25˚C  
Pin Configuration  
Logic Block Diagrams  
SSOP/TSSOP  
Top View  
OE  
1
OE  
Q
LE  
1
1
1
2
56  
55  
D
1
1
1
2
1
1
LE  
1
Q
D
2
1
3
4
54  
53  
GND  
GND  
D
D
1
1
1
1
3
4
5
6
7
8
9
52  
51  
50  
49  
48  
1
3
Q
Q
D
C
D
1
4
Q
1
1
V
CC  
V
CC  
Q
D
D
D
1
5
6
1
1
1
5
6
7
Q
1
Q
7
1
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
Q
GND  
D
TO 9 OTHER CHANNELS  
1
1
8
9
FCT16841-1  
1
1
1
8
Q
D
D
9
OE  
2
Q
10  
1
10  
Q
1
D
D
D
2
2
2
2
1
2
3
LE  
2
Q
2
2
3
Q
2
D
1
2
GND  
D
GND  
D
C
2
2
4
5
Q
4
Q
5
2
2
Q
1
2
D
D
Q
6
2
6
2
V
CC  
V
CC  
Q
D
7
2
7
8
2
2
D
8
Q
2
TO 9 OTHER CHANNELS  
GND  
GND  
FCT16841-2  
Q
9
D
D
2
2
2
2
9
Q
10  
2
10  
OE  
LE  
2
FCT16841-3  
Copyright © 2000, Texas Instruments Incorporated  
123456

中文翻译

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