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CY74FCT162646TPVC PDF预览

CY74FCT162646TPVC

更新时间: 2024-11-25 14:48:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
8页 140K
描述
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.300 INCH, 0.025 INCH PITCH, SSOP-56

CY74FCT162646TPVC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP56,.4
针数:56Reach Compliance Code:not_compliant
风险等级:5.17其他特性:WITH DIRECTION CONTROL
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:FCTJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:18.415 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP56,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:5 VProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:2.794 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
翻译:N/A触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

CY74FCT162646TPVC 数据手册

 浏览型号CY74FCT162646TPVC的Datasheet PDF文件第2页浏览型号CY74FCT162646TPVC的Datasheet PDF文件第3页浏览型号CY74FCT162646TPVC的Datasheet PDF文件第4页浏览型号CY74FCT162646TPVC的Datasheet PDF文件第5页浏览型号CY74FCT162646TPVC的Datasheet PDF文件第6页浏览型号CY74FCT162646TPVC的Datasheet PDF文件第7页 
2646T  
fax id: 7043  
CY74FCT16646T  
CY74FCT162646T  
16-Bit Registered Transceiver  
Features  
Functional Description  
• Low power, pin-compatible replacement for ABT  
functions  
• FCT-E speed at 3.8 ns  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Typical output skew < 250 ps  
• ESD > 2000V  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
The CY74FCT16646T and CY74FCT162646T 16-bit trans-  
ceivers are three-state, D-type registers, and control circuitry  
arranged for multiplexed transmission of data directly from the  
input bus or from the internal registers. Data on the A or B bus  
will be clocked into the registers as the appropriate clock pin  
goes to a HIGH logic level. Output Enable (OE) and direction  
pins (DIR) are provided to control the transceiver function. In  
the transceiver mode, data present at the high impedance port  
may be stored in either the A or B register, or in both. The  
select controls can multiplex stored and real-time (transparent  
mode) data. The direction control determines which bus will  
receive data when the Output Enable (OE) is Active LOW. In  
the isolation mode (Output Enable (OE) HIGH), A data may be  
stored in the B register and/or B data may be stored in the A  
register. The output buffers are designed with a power-off dis-  
able feature that allows live insertion of boards.  
• Industrial temperature range of 40°C to +85°C  
• V = 5V 10%  
±
CC  
CY74FCT16646T Features:  
• 64 mA sink current, 32 mA source current  
The CY74FCT16646T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
• Typical V  
(ground bounce) <1.0V at V = 5V,  
CC  
OLP  
T = 25°C  
A
The CY74FCT162646T has 24-mA balanced output drivers  
with current limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162646T is ideal for driving transmission lines.  
CY74FCT162646T Features:  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical V  
(ground bounce) <0.6V at V = 5V,  
CC  
OLP  
T = 25°C  
A
Logic Block Diagrams  
OE  
2
OE  
1
DIR  
2
DIR  
CLKBA  
SBA  
CLKAB  
1
CLKBA  
2
1
SBA  
CLKAB  
2
1
2
1
SAB  
2
SAB  
1
B REG  
D
B REG  
D
C
C
A
2 1  
A REG  
D
B
2
1
A REG  
D
B
1
1
A
1 1  
C
C
FCT16646-2  
TO 7 OTHER CHANNELS  
FCT16646-1  
TO 7 OTHER CHANNELS  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
August 1994 - Revised October 30, 1997  

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