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CY62256LL-55ZXIT

更新时间： 2024-11-09 12:59:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
12页 395K
描述
Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28

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中文翻译

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CY62256LL-55ZXIT 技术参数

生命周期：Obsolete零件包装代码：TSOP
包装说明：TSOP1,针数：28
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.48
Is Samacsys：N最长访问时间：55 ns
JESD-30 代码：R-PDSO-G28JESD-609代码：e3/e4
长度：11.8 mm内存密度：262144 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：28
字数：32768 words字数代码：32000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：32KX8
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN/NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.55 mm
端子位置：DUAL宽度：8 mm
Base Number Matches：1

CY62256LL-55ZXIT 数据手册

 浏览型号CY62256LL-55ZXIT的Datasheet PDF文件第2页浏览型号CY62256LL-55ZXIT的Datasheet PDF文件第3页浏览型号CY62256LL-55ZXIT的Datasheet PDF文件第4页浏览型号CY62256LL-55ZXIT的Datasheet PDF文件第5页浏览型号CY62256LL-55ZXIT的Datasheet PDF文件第6页浏览型号CY62256LL-55ZXIT的Datasheet PDF文件第7页 
CY62256  
256K (32K x 8) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
—Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• High speed: 55 ns and 70 ns  
The CY62256 is a high-performance CMOS static RAM  
organized as 32K words by 8 bits. Easy memory expansion is  
provided by an active LOW chip enable (CE) and active LOW  
output enable (OE) and three-state drivers. This device has an  
automatic power-down feature, reducing the power  
consumption by 99.9% when deselected.  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
• Voltage range: 4.5V–5.5V operation  
• Low active power (70 ns, LL version, Com’l and Ind’l)  
— 275 mW (max.)  
• Low standby power (70 ns, LL version, Com’l and Ind’l)  
— 28 µW (max.)  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Package available in a standard 450-mil-wide (300-mil  
body width) 28-lead narrow SOIC, 28-lead TSOP-1,  
28-lead reverse TSOP-1, and 600-mil 28-lead PDIP  
packages  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUTBUFFER  
A
10  
A
9
A
8
A
7
A
6
512 x 512  
ARRAY  
A
5
A
4
3
2
A
A
CE  
POWER  
DOWN  
COLUMN  
WE  
DECODER  
I/O  
7
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05248 Rev. *C  
Revised June 25, 2004  
1234567...12

中文翻译

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