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CY62256-70SNCT PDF预览

CY62256-70SNCT

更新时间: 2024-01-30 22:49:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
13页 323K
描述
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, SOIC-28

CY62256-70SNCT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, SOIC-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.09Is Samacsys:N
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:17.9324 mm内存密度:262144 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:1功能数量:1
端口数量:1端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.5封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:2.794 mm
最大待机电流:0.005 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.055 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5057 mm
Base Number Matches:1

CY62256-70SNCT 数据手册

 浏览型号CY62256-70SNCT的Datasheet PDF文件第2页浏览型号CY62256-70SNCT的Datasheet PDF文件第3页浏览型号CY62256-70SNCT的Datasheet PDF文件第4页浏览型号CY62256-70SNCT的Datasheet PDF文件第5页浏览型号CY62256-70SNCT的Datasheet PDF文件第6页浏览型号CY62256-70SNCT的Datasheet PDF文件第7页 
CY62256  
256K (32K x 8) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY62256 is a high-performance CMOS static RAM  
organized as 32K words by 8 bits. Easy memory expansion is  
provided by an active LOW chip enable (CE) and active LOW  
output enable (OE) and three-state drivers. This device has an  
automatic power-down feature, reducing the power  
consumption by 99.9% when deselected.  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• High speed: 55 ns and 70 ns  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
• Voltage range: 4.5V–5.5V operation  
• Low active power (70 ns, LL version, Com’l and Ind’l)  
— 275 mW (max.)  
• Low standby power (70 ns, LL version, Com’l and Ind’l)  
28 µW (max.)  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
• Package available in a standard 450-mil-wide (300-mil  
body width) 28-lead narrow SOIC, 28-lead TSOP-1,  
28-lead reverse TSOP-1, and 600-mil 28-lead PDIP  
packages  
• Also available in Lead-free packages  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUTBUFFER  
A
A
A
10  
9
8
A
7
6
5
A
512 x 512  
ARRAY  
A
A
A
A
4
3
2
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05248 Rev. *E  
• 198 Champion Court  
San Jose, CA 95134  
408-943-2600  
Revised July 14, 2005  

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