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CY62158EV30LL-45ZSXI

更新时间： 2024-09-16 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 997K
描述
8-Mbit (1024K x 8) Static RAM

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中文翻译

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CY62158EV30LL-45ZSXI 数据手册

 浏览型号CY62158EV30LL-45ZSXI的Datasheet PDF文件第2页浏览型号CY62158EV30LL-45ZSXI的Datasheet PDF文件第3页浏览型号CY62158EV30LL-45ZSXI的Datasheet PDF文件第4页浏览型号CY62158EV30LL-45ZSXI的Datasheet PDF文件第5页浏览型号CY62158EV30LL-45ZSXI的Datasheet PDF文件第6页浏览型号CY62158EV30LL-45ZSXI的Datasheet PDF文件第7页 
CY62158EV30 MoBL®  
8-Mbit (1024K x 8) Static RAM  
Features  
Functional Description [2]  
• Very high speed: 45 ns  
The CY62158EV30 is a high performance CMOS static RAM  
organized as 1024K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption. Placing the device into standby  
mode reduces power consumption significantly when  
deselected (CE1 HIGH or CE2 LOW). The eight input and  
output pins (IO0 through IO7) are placed in a high impedance  
state when the device is deselected (CE1 HIGH or CE2 LOW),  
the outputs are disabled (OE HIGH), or a write operation is in  
progress (CE1 LOW and CE2 HIGH and WE LOW).  
— Wide voltage range: 2.20V–3.60V  
• Pin compatible with CY62158DV30  
• Ultra low standby power  
— Typical standby current: 2 µA  
— Maximum standby current: 8 µA  
• Ultra low active power  
— Typical active current: 1.8 mA @ f = 1 MHz  
• Easy memory expansion with CE1, CE2, and OE features  
• Automatic power down when deselected  
• CMOS for optimum speed/power  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. Data on the eight  
IO pins (IO0 through IO7) is then written into the location  
specified on the address pins (A0 through A19).  
• Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and  
48-pin TSOP I packages[1]  
To read from the device, take Chip Enables (CE1 LOW and  
CE2 HIGH) and OE LOW while forcing the WE HIGH. Under  
these conditions, the contents of the memory location  
specified by the address pins appear on the IO pins. See the  
“Truth Table” on page 8 for a complete description of read and  
write modes.  
Logic Block Diagram  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
0
DATA IN DRIVERS  
IO  
1
IO  
2
1024K x 8  
ARRAY  
IO  
3
IO  
IO  
IO  
IO  
4
5
6
7
A
A
A
A
9
10  
11  
12  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Notes  
1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.  
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05578 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 19, 2007  
[+] Feedback  
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CY62158EV30LL-45ZSXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62157EV30LL-45ZSXIT CYPRESS

类似代替

 Standard SRAM, 512KX16, 45ns, CMOS, PDSO44, TSOP2-44
CY62158ELL-45ZSXI CYPRESS

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 8-Mbit (1M x 8) Static RAM
CY62157EV30LL-45ZSXI CYPRESS

类似代替

 8-Mbit (512K x 16) Static RAM

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