Datasheet > CY62158EV30_09

CY62158EV30_09

更新时间： 2024-09-16 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	989K
描述
8-Mbit (1024K x 8) Static RAM

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CY62158EV30_09 数据手册

CY62158EV30 MoBL^®

8-Mbit (1024K x 8) Static RAM

Features

Functional Description ^[2]

• Very high speed: 45 ns

The CY62158EV30 is a high performance CMOS static RAM

organized as 1024K words by 8 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption. Placing the device into standby

mode reduces power consumption significantly when

deselected (CE₁HIGH or CE₂LOW). The eight input and

output pins (IO₀through IO₇) are placed in a high impedance

state when the device is deselected (CE₁HIGH or CE₂LOW),

the outputs are disabled (OE HIGH), or a write operation is in

progress (CE₁LOW and CE₂HIGH and WE LOW).

— Wide voltage range: 2.20V–3.60V

• Pin compatible with CY62158DV30

• Ultra low standby power

— Typical standby current: 2 µA

— Maximum standby current: 8 µA

• Ultra low active power

— Typical active current: 1.8 mA @ f = 1 MHz

• Easy memory expansion with CE₁, CE₂, and OE features

• Automatic power down when deselected

• CMOS for optimum speed/power

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. Data on the eight

IO pins (IO₀through IO₇) is then written into the location

specified on the address pins (A₀through A₁₉).

• Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and

48-pin TSOP I packages^[1]

To read from the device, take Chip Enables (CE₁LOW and

CE₂HIGH) and OE LOW while forcing the WE HIGH. Under

these conditions, the contents of the memory location

specified by the address pins appear on the IO pins. See the

“Truth Table” on page 8 for a complete description of read and

write modes.

Logic Block Diagram

DATA IN DRIVERS

1024K x 8

ARRAY

POWER

DOWN

COLUMN DECODER

Notes

1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.

2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05578 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 19, 2007

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与CY62158EV30_09相关器件

型号	品牌	获取价格	描述	数据表
CY62158EV30_11	CYPRESS	获取价格	8-Mbit (1024 K x 8) Static RAM Automatic power down when deselected
CY62158EV30LL-45BVXI	CYPRESS	获取价格	8-Mbit (1024K x 8) Static RAM
CY62158EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62158EV30LL-45BVXIT	CYPRESS	获取价格	Standard SRAM, 1MX8, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62158EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62158EV30LL-45ZSXI	CYPRESS	获取价格	8-Mbit (1024K x 8) Static RAM
CY62158EV30LL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62158EV30LL-45ZSXIT	CYPRESS	获取价格	Standard SRAM, 1MX8, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62158EV30LL-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY62158EV30LL-45ZXI	CYPRESS	获取价格	Standard SRAM, 1MX8, 45ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, TS

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