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CY62157EV30LL-55ZXET PDF预览

CY62157EV30LL-55ZXET

更新时间： 2024-11-27 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
21页 459K
描述
Standard SRAM, 512KX16, 55ns, CMOS, PDSO48, TSOP1-48

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CY62157EV30LL-55ZXET 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：TSOP1, TSSOP48,.8,20
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.56
最长访问时间：55 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：18.4 mm内存密度：8388608 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-40 °C
组织：512KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装等效代码：TSSOP48,.8,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.00003 A最小待机电流：1.5 V
子类别：SRAMs最大压摆率：0.035 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：12 mm
Base Number Matches：1

CY62157EV30LL-55ZXET 数据手册

 浏览型号CY62157EV30LL-55ZXET的Datasheet PDF文件第2页浏览型号CY62157EV30LL-55ZXET的Datasheet PDF文件第3页浏览型号CY62157EV30LL-55ZXET的Datasheet PDF文件第4页浏览型号CY62157EV30LL-55ZXET的Datasheet PDF文件第5页浏览型号CY62157EV30LL-55ZXET的Datasheet PDF文件第6页浏览型号CY62157EV30LL-55ZXET的Datasheet PDF文件第7页 
CY62157EV30 MoBL®  
8-Mbit (512 K × 16) Static RAM  
8-Mbit (512  
K × 16) Static RAM  
Features  
Functional Description  
■ Thin small outline package (TSOP) I package configurable as  
512 K × 16 or 1 M × 8 static RAM (SRAM)  
The CY62157EV30 is a high performance CMOS static RAM  
organized as 512K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Place the device  
into standby mode when deselected (CE1 HIGH or CE2 LOW or  
both BHE and BLE are HIGH). The input or output pins (I/O0  
through I/O15) are placed in a high impedance state when the  
device is deselected (CE1HIGH or CE2 LOW), the outputs are  
disabled (OE HIGH), Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH), or a write operation is active (CE1  
LOW, CE2 HIGH and WE LOW).  
■ High speed: 45 ns  
■ Temperature ranges  
❐ Industrial: –40 °C to +85 °C  
❐ Automotive-A: –40 °C to +85 °C  
❐ Automotive-E: –40 °C to +125 °C  
■ Wide voltage range: 2.20 V to 3.60 V  
■ Pin compatible with CY62157DV30  
■ Ultra low standby power  
❐ Typical standby current: 2 A  
❐ Maximum standby current: 8 A (Industrial)  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is  
written into the location specified on the address pins (A0 through  
■ Ultra low active power  
❐ Typical active current: 1.8 mA at f = 1 MHz  
A
18). If Byte High Enable (BHE) is LOW, then data from I/O pins  
■ Easy memory expansion with CE1, CE2, and OE features  
■ Automatic power down when deselected  
(I/O8 through I/O15) is written into the location specified on the  
address pins (A0 through A18).  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appear  
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on I/O8 to I/O15. See Truth Table on page 13  
for a complete description of read and write modes.  
■ Complementary Metal Oxide Semiconductor (CMOS) for  
optimum speed and power  
■ Available in Pb-free and non Pb-free 48-ball very fine-pitch ball  
grid array (VFBGA), Pb-free 44-pin TSOP II and 48-pin TSOP I  
packages  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
512 K × 16/1 M x 8  
RAM Array  
I/O0–I/O7  
A 3  
I/O8–I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BYTE  
CE  
CE  
2
BHE  
WE  
1
PowerDown  
Circuit  
CE2  
CE  
BHE  
BLE  
1
OE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05445 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 30, 2011  
[+] Feedback  
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中文翻译

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CY62157EV30LL-55ZXET 替代型号

型号 品牌 替代类型 描述 数据表
CY62157EV30LL-55ZXE CYPRESS

完全替代

 8 Mbit (512K x 16) Static RAM

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