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CY62148L-70SCT PDF预览

CY62148L-70SCT

更新时间: 2024-11-05 21:01:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 187K
描述
Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, 0.450 INCH, PLASTIC, SOIC-32

CY62148L-70SCT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.450 INCH, PLASTIC, SOIC-32
针数:32Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.68最长访问时间:70 ns
JESD-30 代码:R-PDSO-G32JESD-609代码:e0
长度:20.447 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端口数量:1端子数量:32
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):220
认证状态:Not Qualified座面最大高度:2.9972 mm
最小待机电流:2 V最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:11.303 mmBase Number Matches:1

CY62148L-70SCT 数据手册

 浏览型号CY62148L-70SCT的Datasheet PDF文件第2页浏览型号CY62148L-70SCT的Datasheet PDF文件第3页浏览型号CY62148L-70SCT的Datasheet PDF文件第4页浏览型号CY62148L-70SCT的Datasheet PDF文件第5页浏览型号CY62148L-70SCT的Datasheet PDF文件第6页浏览型号CY62148L-70SCT的Datasheet PDF文件第7页 
MoBL  
CY62148V MoBL™  
512K x 8 MoBL Static RAM  
The device can be put into standby mode when deselected  
(CE HIGH).  
Features  
• Low voltage range:  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O through I/O ) is then written into the location speci-  
— 2.7V–3.6V  
• Ultra low active power  
• Low standby power  
0
7
fied on the address pins (A through A ).  
0
18  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Functional Description  
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
The CY62148V is a high-performance CMOS static RAM or-  
ganized as 524,288 words by 8 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL™) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
power consumption by 99% when addresses are not toggling.  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW and WE LOW).  
The CY62148V is available in a 36-ball FBGA, 32 pin TSOPII,  
and a 32-pin SOIC package.  
Logic Block Diagram  
I/O  
0
1
2
Data in Drivers  
I/O  
I/O  
A
A
0
6
1
A
2
A
3
A
4
I/O  
I/O  
I/O  
3
4
5
6
512K x 8  
ARRAY  
A
5
A
A
A
A
7
8
9
I/O  
I/O  
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
7
62148V-1  
OE  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Cypress Semiconductor Corporation  
March 23, 2000