Datasheet > CY62148L-100ZSC

CY62148L-100ZSC

更新时间： 2024-09-23 23:45:07

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
9页	220K
描述
x8 SRAM

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数据手册

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CY62148L-100ZSC 数据手册

1CY62148

CY62148

512K x 8 Static RAM

an automatic power-down feature that reduces power con-

sumption by more than 99% when deselected.

Features

• 4.5V − 5.5V operation

• CMOS for optimum speed/power

• Low active power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location speci-

fied on the address pins (A₀through A₁₈).

— 660 mW (max.)

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH for read. Under these conditions, the con-

tents of the memory location specified by the address pins will

appear on the I/O pins.

• Low standby power (L version)

— 2.75 mW (max.)

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE options

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

Functional Description

The CY62148 is a high-performance CMOS static RAM orga-

nized as 524,288 words by 8 bits. Easy memory expansion is

provided by an active LOW Chip Enable (CE), an active LOW

Output Enable (OE), and three-state drivers. This device has

The CY62148 is available in a standard 32 pin 450-mil-wide

body width SOIC and 32 pin TSOP II packages.

Logic Block Diagram

Configuration

Top View

SOIC

TSOP II

V_CC

I/O

INPUT BUFFER

I/O

512 x 256 x 8

ARRAY

I/O

GND

I/O

POWER

DOWN

COLUMN

DECODER

I/O

62148-1

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 14, 2001

12 3 4 5 6 7...9

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