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CY62148GN30 PDF预览

CY62148GN30

更新时间: 2024-02-21 08:42:50
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
16页 928K
描述
4-Mbit (512K × 8) Static RAM

CY62148GN30 数据手册

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CY62148GN MoBL®  
4-Mbit (512K × 8) Static RAM  
4-Mbit (512K  
× 8) Static RAM  
applications. The device also has an automatic power-down  
feature that significantly reduces power consumption when  
addresses are not toggling. Placing the device in standby mode  
reduces power consumption by more than 99% when deselected  
(CE HIGH). The eight input and output pins (I/O0 through I/O7)  
are placed in a high-impedance state when the device is  
deselected (CE HIGH), Outputs are disabled (OE HIGH), or  
during an active Write operation (CE LOW and WE LOW).  
Features  
Very high speed: 45 ns  
Wide voltage range: 2.2 V to 3.6 V, 4.5 V to 5.5 V  
Ultra low standby power  
Typical standby current: 3.5 µA  
Maximum standby current: 8.7 µA  
Easy memory expansion with CE and OE features  
Automatic power-down when deselected  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address pins (A0  
through A18).  
Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under  
these conditions, the contents of the memory location specified  
by the address pins appear on the I/O pins.  
Available in Pb-free 32-pin thin small outline package (TSOP) II  
and 32-pin small-outline integrated circuit (SOIC) packages  
Functional Description  
For a complete list of related documentation, click here.  
The CY62148GN is a high-performance CMOS static RAM  
organized as 512K words by 8-bits. This device features  
advanced circuit design to provide ultra low standby current. This  
is ideal for providing More Battery Life™ (MoBL) in portable  
Logic Block Diagram  
A
I/O  
I
0
0
INPUT BUFFER  
A
1
A
2
I/O  
I
1
2
3
4
5
6
7
A
3
A
4
I/O  
I
A
5
A
I/O  
I
6
512K x 8  
A
7
A
I/O  
I
8
ARRAY  
A
9
A
I/O  
I
10  
A
11  
A
I/O  
12  
I
I/O  
CE  
I
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Cypress Semiconductor Corporation  
Document Number: 001-95418 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 19, 2016  

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