CY62148BLL-70ZIT

更新时间： 2024-11-20 13:00:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器光电二极管
页数	文件大小	规格书
11页	191K
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CY62148BLL-70ZIT 数据手册

CY62148B MoBL™

512K x 8 Static RAM

an automatic power-down feature that reduces power con-

sumption by more than 99% when deselected.

Features

• 4.5V–5.5V operation

• Low active power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location speci-

fied on the address pins (A₀through A₁₈).

— Typical active current: 2.5 mA @ f = 1 MHz

— Typical active current: 12.5 mA @ f = f_max

• Low standby current

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

• CMOS for optimum speed/power

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH for read. Under these conditions, the con-

tents of the memory location specified by the address pins will

appear on the I/O pins.

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

Functional Description

The CY62148B is a high-performance CMOS static RAM or-

ganized as 512K words by 8 bits. Easy memory expansion is

provided by an active LOW Chip Enable (CE), an active LOW

Output Enable (OE), and three-state drivers. This device has

The CY62148B is available in a standard 32-pin 450-mil-wide

body width SOIC, 32-pin TSOP II, and 32-pin Reverse TSOP

II packages.

Logic Block Diagram

Configuration

Top View

SOIC

TSOP II

V_CC

A₁₅

A₁₈

A₁₇

A₁₆

A₁₄

A₁₂

A₇

A₆

A₁₃

A₈

A₅

A₉

I/O

A₄

A₃

A₂

A₁₁

INPUT BUFFER

A₁₀

I/O₇

I/O₆

I/O₅

I/O₄

I/O₃

I/O

A₁

A₀

I/O₀

I/O₁

I/O₂

GND

I/O

512 x 256 x 8

ARRAY

Top View

Reverse

TSOP II

I/O₃

GND

I/O₂

I/O₁

I/O

I/O₄

I/O₅

POWER

DOWN

COLUMN

DECODER

I/O₀

I/O₆

I/O₇

I/O

A₀

A₁

A₂

A₃

A₄

A₅

A₆

A₇

A₁₂

23 A₁₀

A₁₁

A₉

A₈

A₁₃

A₁₈

A₁₅

V_cc

A₁₄

A₁₆

A₁₇

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05039 Rev. *B

October 8, 2001

12 3 4 5 6 7...11

中文翻译

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CY62148BLL-70ZIT 替代型号

型号	品牌	替代类型	描述	数据表
CY62148BLL-70ZC	CYPRESS	完全替代	512K x 8 Static RAM

与CY62148BLL-70ZIT相关器件

型号	品牌	获取价格	描述	数据表
CY62148BLL-70ZRC	CYPRESS	获取价格	512K x 8 Static RAM
CY62148BLL-70ZRCT	CYPRESS	获取价格	Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, REVERSE, TSOP2-32
CY62148BLL-70ZRI	ROCHESTER	获取价格	Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, REVERSE, TSOP2-32
CY62148BLL-70ZRI	CYPRESS	获取价格	512K x 8 Static RAM
CY62148BLL-70ZRIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, REVERSE, TSOP2-32
CY62148BLL-70ZRIT	ROCHESTER	获取价格	Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, REVERSE, TSOP2-32
CY62148BN	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148BN_09	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148BN_10	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148BNLL	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM

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