5秒后页面跳转
捷配首页

Datasheet > CY62147VL-70ZI
CY62147VL-70ZI PDF预览

CY62147VL-70ZI

更新时间： 2024-11-24 10:44:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 198K
描述
Standard SRAM, 256KX16, 150ns, CMOS, PDSO44, TSOP2-44

阅读下载

中文翻译

获取价格

CY62147VL-70ZI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2-44针数：44
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.87
最长访问时间：150 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44JESD-609代码：e0
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：44
字数：262144 words字数代码：256000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：TSOP44,.46,32
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：2/3.3 V认证状态：Not Qualified
最大待机电流：0.0000055 A最小待机电流：1 V
子类别：SRAMs最大压摆率：0.015 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30

CY62147VL-70ZI 数据手册

 浏览型号CY62147VL-70ZI的Datasheet PDF文件第2页浏览型号CY62147VL-70ZI的Datasheet PDF文件第3页浏览型号CY62147VL-70ZI的Datasheet PDF文件第4页浏览型号CY62147VL-70ZI的Datasheet PDF文件第5页浏览型号CY62147VL-70ZI的Datasheet PDF文件第6页浏览型号CY62147VL-70ZI的Datasheet PDF文件第7页 
PRELIMINARY  
CY62147V MoBL™  
256K x 16 Static RAM  
disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Features  
• Low voltage range:  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
1.8V–3.6V  
—
• Ultra low active, standby power  
0
7
written into the location specified on the address pins (A  
0
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
through A ). If Byte High Enable (BHE) is LOW, then data  
17  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
17  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
Functional Description  
The CY62147V is a high-performance CMOS static RAM or-  
ganized as 262,144 words by 16 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL™) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
power consumption by 99% when addresses are not toggling.  
The device can also be put into standby mode when deselec-  
tected (CE HIGH) or when CE is LOW and both BLE and BHE  
pins will appear on I/O to I/O . If Byte High Enable (BHE) is  
0
7
LOW, then data from memory will appear on I/O to I/O . See  
8
15  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
The 62147V MoBL SRAM has an extremely wide operating  
voltage range. The datasheet has been specified to accurately  
describe the device behavior at three common voltage ranges  
(3.6 – 2.7, 2.7 – 2.3, 2.3 – 1.8)  
are HIGH. The input/output pins (I/O through I/O ) are  
placed in a high impedance state when: deselected (CE  
HIGH), outputs are disabled (OE HIGH), BHE and BLE are  
0
15  
The CY62147V is available in 48-ball FBGA and standard  
44-pin TSOP Type II (forward pinout) packaging.  
Logic Block Diagram  
Pin  
Configurations  
TSOP II (Forward)  
Top View  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
DATA IN DRIVERS  
A
A
2
7
OE  
A
1
A9  
BHE  
BLE  
I/O  
I/O  
I/O  
A
0
A8  
A7  
A6  
A5  
A4  
A3  
CE  
I/O  
7
0
15  
37  
36  
35  
34  
33  
I/O  
I/O  
8
1
2
14  
13  
12  
256K x 16  
9
10  
11  
12  
13  
I/O  
V
SS  
RAM Array  
1024 X 4096  
I/O  
I/O0 – I/O7  
I/O8 – I/O15  
3
CC  
V
SS  
V
V
CC  
A2  
A1  
A0  
I/O  
32  
I/O  
I/O  
4
5
6
7
11  
10  
I/O  
I/O  
I/O  
31  
30  
29  
28  
14  
15  
16  
I/O  
I/O  
9
8
WE 17  
NC  
18  
27  
26  
25  
A
A
8
16  
A
19  
A
9
COLUMN DECODER  
15  
A
20  
21  
22  
A
14  
10  
A
A
12  
24  
23  
11  
13  
A
A
17  
BHE  
WE  
CE  
62147V–2  
OE  
BLE  
CE  
Power Down  
Circuit  
62147V–1  
BHE  
BLE  
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
July 16, 1999  
1234567...11

中文翻译

下载PDF

与CY62147VL-70ZI相关器件

型号 品牌 获取价格 描述 数据表
CY62147VLL-70BAI ETC

获取价格

 		SRAM|256KX16|CMOS|BGA|48PIN|PLASTIC
CY62147VLL-70ZI CYPRESS

获取价格

 		4M (256K x 16) Static RAM
CY62147VLL-70ZIT CYPRESS

获取价格

 		Standard SRAM, 256KX16, 70ns, CMOS, PDSO44, TSOP2-44
CY62148 CYPRESS

获取价格

 		512K x 8 MoBL Static RAM
CY62148-100SC ETC

获取价格

 		x8 SRAM
CY62148-100SI ETC

获取价格

 		x8 SRAM
CY62148-100ZSC ETC

获取价格

 		x8 SRAM
CY62148-100ZSI ETC

获取价格

 		x8 SRAM
CY62148-55 CYPRESS

获取价格

 		512K x 8 Static RAM
CY62148-55SC CYPRESS

获取价格

 		512K x 8 Static RAM

与CY62147VL-70ZI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证