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CY62147GE18-55ZSXI PDF预览

CY62147GE18-55ZSXI

更新时间： 2024-11-19 19:42:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
22页 479K
描述
Standard SRAM, 256KX16, 55ns, CMOS, PDSO44, TSOP2-44

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CY62147GE18-55ZSXI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TSOP2,Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：2.18
最长访问时间：55 nsJESD-30 代码：R-PDSO-G44
长度：18.415 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：44
字数：262144 words字数代码：256000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.194 mm最大供电电压 (Vsup)：2.2 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10.16 mm
Base Number Matches：1

CY62147GE18-55ZSXI 数据手册

 浏览型号CY62147GE18-55ZSXI的Datasheet PDF文件第2页浏览型号CY62147GE18-55ZSXI的Datasheet PDF文件第3页浏览型号CY62147GE18-55ZSXI的Datasheet PDF文件第4页浏览型号CY62147GE18-55ZSXI的Datasheet PDF文件第5页浏览型号CY62147GE18-55ZSXI的Datasheet PDF文件第6页浏览型号CY62147GE18-55ZSXI的Datasheet PDF文件第7页 
CY62147G/CY621472G  
CY62147GE MoBL®  
4-Mbit (256K words × 16-bit) Static RAM  
with Error-Correcting Code (ECC)  
4-Mbit (256K words  
× 16-bit) Static RAM with Error-Correcting Code (ECC)  
Data writes are performed by asserting the Write Enable (WE)  
input LOW, while providing the data on I/O0 through I/O15 and  
address on A0 through A17 pins. The Byte High Enable (BHE)  
and Byte Low Enable (BLE) inputs control write operations to the  
upper and lower bytes of the specified memory location. BHE  
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.  
Features  
■ High speed: 45 ns/55 ns  
■ Ultra-low standby power  
❐ Typical standby current: 3.5 A  
❐ Maximum standby current: 8.7 A  
Data reads are performed by asserting the Output Enable (OE)  
input and providing the required address on the address lines.  
Read data is accessible on the I/O lines (I/O0 through I/O15).  
Byte accesses can be performed by asserting the required byte  
enable signal (BHE or BLE) to read either the upper byte or the  
lower byte of data from the specified address location.  
■ Embedded ECC for single-bit error correction[1]  
■ Wide voltage range: 1.65V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V  
■ 1.0-V data retention  
■ TTL-compatible inputs and outputs  
■ Error indication (ERR) pin to indicate 1-bit error detection and  
correction  
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the  
device is deselected (CE HIGH for a single chip enable device  
and CE1 HIGH/CE2 LOW for a dual chip enable device), or  
control signals are deasserted (OE, BLE, BHE).  
■ Pb-free 48-ball VFBGA and 44-pin TSOP II packages  
Functional Description  
The device also has a unique Byte Power down feature, where,  
if both the Byte Enables (BHE and BLE) are disabled, the  
devices seamlessly switch to standby mode irrespective of the  
state of the chip enables, thereby saving power.  
CY62147G and CY62147GE are high-performance CMOS  
low-power (MoBL) SRAM devices with embedded ECC. Both  
devices are offered in single and dual chip enable options and in  
multiple pin configurations. The CY62147GE device includes an  
ERR pin that signals an error-detection and correction event  
during a read cycle.  
On the CY62147GE devices, the detection and correction of a  
single-bit error in the accessed location is indicated by the  
assertion of the ERR output (ERR = HIGH)[1]. See the Truth  
Table – CY62147G/CY62147GE on page 16 for a complete  
description of read and write modes.  
Devices with a single chip enable input are accessed by  
asserting the chip enable (CE) input LOW. Dual chip enable  
devices are accessed by asserting both chip enable inputs – CE1  
as low and CE2 as HIGH.  
The logic block diagrams are on page 2.  
Product Portfolio  
Power Dissipation  
Features and  
Options  
(see the Pin  
Configurations  
section)  
Operating ICC, (mA)  
Standby, ISB2 (µA)  
Product[2]  
Range  
VCC Range (V) Speed (ns)  
f = fmax  
Typ[3]  
Max  
Typ[3]  
Max  
CY62147G(E)18  
Industrial  
1.65 V–2.2 V  
2.2 V–3.6 V  
55  
45  
15  
15  
20  
20  
3.5  
3.5  
10  
Single or dual  
Chip Enables  
CY62147G(E)30  
CY621472G30  
8.7  
Optional ERR  
pin  
CY62147G(E)  
4.5 V–5.5 V  
Notes  
1. This device does not support automatic write-back on error detection.  
2. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 17.  
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),  
CC  
CC  
V
= 3 V (for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.  
CC  
CC CC CC A  
Cypress Semiconductor Corporation  
Document Number: 001-92847 Rev. *J  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 27, 2017  
 
 
 
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