Datasheet > CY62147G30-45BVXAT

CY62147G30-45BVXAT

更新时间： 2024-11-06 14:56:39

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
20页	585K
描述
Asynchronous SRAM

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CY62147G/CY621472G

MoBL^®Automotive

4-Mbit (256K words × 16-bit) Static RAM

with Error-Correcting Code (ECC)

4-Mbit (256K words

× 16-bit) Static RAM with Error-Correcting Code (ECC)

Data writes are performed by asserting the Write Enable (WE)

input LOW, while providing the data on I/O₀through I/O₁₅and

address on A₀through A₁₇pins. The Byte High Enable (BHE)

and Byte Low Enable (BLE) inputs control write operations to the

upper and lower bytes of the specified memory location. BHE

controls I/O₈through I/O₁₅and BLE controls I/O₀through I/O₇.

Features

■ High speed: 45 ns/55 ns

■ Temperature Ranges

❐ Automotive-A: -40 C to +85 C

❐ Automotive-E: -40 C to +125 C

■ Ultra-low standby power

❐ Typical standby current: 3.5 A

■ Embedded ECC for single-bit error correction^{[1, 2]}

Data reads are performed by asserting the Output Enable (OE)

input and providing the required address on the address lines.

Read data is accessible on the I/O lines (I/O₀through I/O₁₅).

Byte accesses can be performed by asserting the required byte

enable signal (BHE or BLE) to read either the upper byte or the

lower byte of data from the specified address location.

■ Wide voltage range: 2.2 V to 3.6 V

■ 1.0-V data retention

■ TTL-compatible inputs and outputs

■ Pb-free 48-ball VFBGA and 44-pin TSOP II packages

All I/Os (I/O₀through I/O₁₅) are placed in a HI-Z state when the

device is deselected (CE HIGH for a single chip enable device

and CE₁HIGH/CE₂LOW for a dual chip enable device), or

control signals are deasserted (OE, BLE, BHE).

Functional Description

The device also has a unique Byte Power down feature, where,

if both the Byte Enables (BHE and BLE) are disabled, the

devices seamlessly switch to standby mode irrespective of the

state of the chip enables, thereby saving power.

CY62147G/CY621472G is high-performance CMOS low-power

(MoBL) SRAM devices with embedded ECC. Both devices are

offered in single and dual chip enable options and in multiple pin

configurations.

Devices with a single chip enable input are accessed by

asserting the chip enable (CE) input LOW. Dual chip enable

devices are accessed by asserting both chip enable inputs – CE₁

as low and CE₂as HIGH.

The logic block diagrams are on page 2.

Notes

1. This device does not support automatic write-back on error detection.

2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details.

Cypress Semiconductor Corporation

Document Number: 001-95424 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 2, 2018

12 3 4 5 6 7...20

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与CY62147G30-45BVXAT相关器件

型号	品牌	获取价格	描述	数据表
CY62147G30-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-45ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-45ZSXAT	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-45ZSXI	CYPRESS	获取价格	Standard SRAM, 256KX16, 45ns, CMOS, PDSO44, TSOP2-44
CY62147G30-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-55BVXE	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-55BVXET	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-55ZSXE	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-55ZSXET	INFINEON	获取价格	Asynchronous SRAM

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