Datasheet > CY62147EV30LL-55ZSXE

CY62147EV30LL-55ZSXE

更新时间： 2024-11-19 03:08:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		内存集成电路静态存储器光电二极管
页数	文件大小	规格书
12页	618K
描述
4-Mbit (256K x 16) Static RAM

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CY62147EV30 MoBL^®

4-Mbit (256K x 16) Static RAM

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption when addresses are not toggling.

Placing the device into standby mode reduces power

consumption by more than 99% when deselected (CE HIGH

or both BLE and BHE are HIGH). The input and output pins

(IO₀through IO₁₅) are placed in a high impedance state when:

Features

• Very high speed: 45 ns

• Temperature ranges

— Industrial: –40°C to +85°C

— Automotive-A: –40°C to +85°C

— Automotive-E: –40°C to +125°C

• Wide voltage range: 2.20V–3.60V

• Pin compatible with CY62147DV30

• Ultra low standby power

• Deselected (CE HIGH)

• Outputs are disabled (OE HIGH)

• Both Byte High Enable and Byte Low Enable are disabled

(BHE, BLE HIGH)

— Typical standby current: 1 µA

— Maximum standby current: 7 µA (Industrial)

• Ultra low active power

• Write operation is active (CE LOW and WE LOW)

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from IO pins (IO₀through IO₇) is written into the location

specified on the address pins (A₀through A₁₇). If Byte High

Enable (BHE) is LOW, then data from IO pins (IO₈through

IO₁₅) is written into the location specified on the address pins

(A₀through A₁₇).

— Typical active current: 2 mA @ f = 1 MHz

• Easy memory expansion with CE and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

• Offered in Pb-free 48-ball VFBGA and 44-pin TSOPII

packages

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH.

If Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on IO₀to IO₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. See the “Truth Table” on page 9 for a

complete description of read and write modes.

• Byte power down feature

Functional Description ^[1]

The CY62147EV30 is a high performance CMOS static RAM

organized as 256K words by 16 bits. This device features

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

256K x 16

RAM Array

IO₀–IO₇

IO₈–IO₁₅

COLUMN DECODER

BHE

POWER DOWN

CIRCUIT

BHE

BLE

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation

Document #: 38-05440 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 6, 2007

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CY62147EV30LL-55ZSXE 替代型号

型号	品牌	替代类型	描述	数据表
CY62147DV30L-55ZSXE	CYPRESS	完全替代	4-Mbit (256K x 16) Static RAM

与CY62147EV30LL-55ZSXE相关器件

型号	品牌	获取价格	描述	数据表
CY62147EV30LL-55ZSXET	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62147G18-55BVXI	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, VFBGA-48
CY62147G18-55BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62147G18-55ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-45B2XI	CYPRESS	获取价格	Standard SRAM, 256KX16, 45ns, CMOS, PBGA48, VFBGA-48
CY62147G30-45B2XI	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-45BVXA	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-45BVXAT	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62147G30-45ZSXA	INFINEON	获取价格	Asynchronous SRAM

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